參數(shù)資料
型號: MAX13342EETD+T
廠商: Maxim Integrated Products
文件頁數(shù): 5/18頁
文件大小: 0K
描述: IC TXRX USB FS 3WIRE 14-TDFN
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
類型: 收發(fā)器
驅(qū)動器/接收器數(shù): 1/1
規(guī)程: USB 2.0
電源電壓: 2.3 V ~ 3.6 V
安裝類型: 表面貼裝
封裝/外殼: 14-WFDFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 14-TDFN-EP(3x3)
包裝: 帶卷 (TR)
MAX13342E/MAX13345E
3-Wire Interface Full-Speed USB Transceivers
With/Without Internal Series Resistors
______________________________________________________________________________________
13
VOHD
VOLD
90%
10%
90%
10%
tFR, tLR
tFF, tLF
Figure 3. Rise and Fall Times
DAT CONNECTED TO
GND, SE0 CONNECTED
TO GND. D+ PULLED TO
3.0V WITH 150
.
DAT CONNECTED TO
VL, SE0 CONNECTED
TO GND. D+ PULLED
TO GND WITH 150
.
DAT CONNECTED TO
VL, SE0 CONNECTED
TO GND. D- PULLED
TO VL WITH 150
.
DAT CONNECTED TO
GND, SE0 CONNECTED
TO GND. D- PULLED
TO GND WITH 150
.
tPZH_DRV
tPZL_DRV
tPZH_DRV
tPZL_DRV
tPHZ_DRV
tPLZ_DRV
tPHZ_DRV
tPLZ_DRV
D+
D-
OE
Figure 5. Enable and Disable Timing, Transmitter
DAT
SEO
D-
D+
tPLH_DRV
tPHL_DRV
VCRS_F , VCRS_L
RISE/FALL TIMES < 4ns
Figure 4. Timing of DAT, SE0 to D+ and D-
Timing Diagrams/Test Circuits
+3V
0V
DAT/SEO
VL
D+/D-
tPLH_RCV,
tPLH_SE
tPHL_RCV,
tPHL_SE
INPUT RISE/FALL TIME < 4ns
Figure 6. D+/D- to DAT, SE0 Propagation Delays
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