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參數(shù)資料
| 型號： | MAX13345EEBC+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 16/18頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TXRX USB FS 3WIRE 12-UCSP |
| 產品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,500 |
| 類型： | 收發(fā)器 |
| 驅動器/接收器數(shù)： | 1/1 |
| 規(guī)程： | USB 2.0 |
| 電源電壓： | 2.3 V ~ 3.6 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 12-WFBGA，WLCSP |
| 供應商設備封裝： | 12-UCSP（3x4） |
| 包裝： | 帶卷 (TR) |
MAX13342E/MAX13345E
3-Wire Interface Full-Speed USB Transceivers
With/Without Internal Series Resistors
_______________________________________________________________________________________
7
Pin Description
PIN
TDFN
UCSP
NAME
FUNCTION
1B1
VTRM
Regulated Output Voltage. VTRM provides a 3.3V output derived from VBUS. Bypass VTRM to GND
with a 1F (min) low-ESR capacitor, such as ceramic or plastic film types. VTRM provides power
to internal circuitry and the internal D+ pullup resistor. Do not use VTRM to power external
circuitry. These USB transceivers can also be powered by an externally regulated 3.3V supply
connected to both VBUS and VTRM.
2A1
VL
System-Side Power-Supply Input. Connect VL to the systems logic-level power supply. Bypass VL
to GND with a 0.1F (min) low-ESR ceramic capacitor.
3
A2
SE0
Logic-Side Data Input/Output. SE0 operates as an input when
OE is low and as an output when
OE is high. As an input, when SE0 is active high, D+ and D- are both driven low. As an output,
SE0 goes active high when both D+ and D- are low. (See Tables 3 and 4.)
4
A3
DAT
Logic-Side Data Input/Output. DAT operates as an input for data on D+/D- when
OE is low. DAT
operates as the output of the differential receiver on D+/D- when
OE is high. (See Tables 3 and 4.)
5, 12
—
N.C.
No Connection. Leave N.C. unconnected. N.C. is not internally connected.
6
B3
SUS
Suspend Input. Drive SUS low for normal transceiver operation. Drive SUS high for low-power
state.
7
A4
BD
USB Detector Output. A high on BD indicates that VBUS is present.
8B4
OE
Output Enable.
OE controls the USB transmitter outputs (D+/D-) and the interface signals (DAT,
SE0) when in USB mode. Drive
OE high to operate D+/D- as inputs and to operate the logic
interface signals as outputs. Drive
OE low to operate D+/D- as outputs and to operate the logic
interface signals as inputs.
9
C4
GND
Ground
10
C3
D-
Negative USB Differential Data Input/Output. D- is wired to the USB connector directly
(MAX13345E) or through a series resistor (MAX13342E). D- operates as an input when
OE is high
and as an output when
OE is low.
11
C2
D+
Positive USB Differential Data Input/Output. D+ is wired to the USB connector directly
(MAX13345E) or through a series resistor (MAX13342E). D+ operates as an input when
OE is
high and as an output when
OE is low.
13
B2
ENUM
Enumerate. Drive ENUM high to connect the internal 1.5k
resistor from D+ to VTRM. Drive ENUM
low to disconnect the internal 1.5k
resistor.
14
C1
VBUS
USB-Side Power-Supply Input. Connect VBUS to the incoming USB power supply. Bypass VBUS to
GND with a 1F ceramic capacitor.
EP
—
EP
Exposed Paddle. Connect EP to GND.
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