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參數(shù)資料
| 型號： | MAX13345EETD+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 3/18頁 |
| 文件大小： | 0K |
| 描述： | IC TXRX USB FS 3WIRE 14-TDFN |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,500 |
| 類型： | 收發(fā)器 |
| 驅(qū)動器/接收器數(shù)： | 1/1 |
| 規(guī)程： | USB 2.0 |
| 電源電壓： | 2.3 V ~ 3.6 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-WFDFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 14-TDFN-EP（3x3） |
| 包裝： | 帶卷 (TR) |
MAX13342E/MAX13345E
3-Wire Interface Full-Speed USB Transceivers
With/Without Internal Series Resistors
______________________________________________________________________________________
11
Applications Information
USB Data Transfer
Transmitting Data
The MAX13342E/MAX13345E transmit USB data to the
USB differentially on D+ and D- when
OE is low. The
D+ and D- outputs are determined by SE0 and DAT
(see Table 3).
Receiving Data
Drive
OE high and SUS low to receive data on D+/D-.
Differential data received on D+ and D- appear at DAT.
SE0 goes high only when both D+ and D- are low
(Table 4).
External Resistors
(MAX13342E)
The MAX13342E provides low internal resistance on
D+/D-. Two external series resistors for impedance
matching are required for USB. Place the resistors in
between the MAX13342E and the USB connector (see
Figure 2).
External Capacitors
Use three external capacitors for proper operation.
Bypass VL to GND with a 0.1F ceramic capacitor.
Bypass VBUS to GND with a 1F ceramic capacitor.
Bypass VTRM to GND with a 1F (min) ceramic or plas-
tic capacitor. Place all capacitors as close to the
device as possible.
UCSP Application Information
For the latest application details on UCSP construction,
dimensions, tape carrier information, printed circuit
board (PCB) techniques, bump-pad layout, and recom-
mended reflow temperature profile, as well as the latest
information on reliability testing results, refer to
Application Note 1891: UCSP—A Wafer-Level Chip-
Scale Package available on Maxim’s website at
www.maxim-ic.com/ucsp.
(
OE = 0, SUS = 0)
INPUTS
OUTPUTS
DAT
SE0
D+
D-
00
01
00
10
11
00
Table 3. Transmit Truth Table
(
OE = 1, SUS = 0)
INPUTS
OUTPUTS
D+
D-
DAT
SE0
0
*DAT
1
0
1
**0
0
1
0
**1
0
11
X
0
Table 4. Receive Truth Table
*Last state
**D+/D- differential receiver output
X = Undefined
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