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參數(shù)資料
| 型號： | MAX13433EETD+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 7/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | TXRX RS-485 16MBPS FULL 14TDFN |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 1 |
| 類型： | 收發(fā)器 |
| 驅(qū)動器/接收器數(shù)： | 1/1 |
| 規(guī)程： | RS485 |
| 電源電壓： | 3 V ~ 5.5 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-WFDFN 裸露焊盤 |
| 供應商設(shè)備封裝： | 14-TDFN-EP（3x3） |
| 包裝： | 標準包裝 |
| 其它名稱： | MAX13433EETD+TDKR |
RS-485 Transceivers with Low-Voltage
Logic Interface
Detailed Description
The MAX13430E–MAX13433E are full- and half-duplex
RS-485 transceivers that feature an adjustable low-
voltage logic interface for application in multivoltage
systems. This allows direct interfacing to low-
voltage ASIC/FPGAs without extra components. The
MAX13430E–MAX13433E RS-485 transceivers operate
with a VCC voltage supply from +3V to +5V. The low-
voltage logic interface operates with a voltage supply
from +1.62V to VCC.
The MAX13430E–MAX13433E are ±30kV ESD-protect-
ed RS-485 transceivers with one driver and one receiv-
er. All devices have a 1/8-unit load receiver input
impedance, allowing up to 256 transceivers on the bus.
These devices include fail-safe circuitry, guaranteeing
a logic-high receiver output when receiver inputs are
open or shorted. The receivers output a logic-high if all
transmitters on a terminated bus are disabled (high
impedance). All devices feature hot-swap capability to
eliminate false transitions on the bus during power-up
or hot insertion.
The MAX13430E/MAX13432E feature reduced slew-
rate drivers that minimize EMI and reduce reflections
caused by improperly terminated cables, allowing
error-free data transmission up to 500kbps. The
MAX13431E/MAX13433E driver slew rates are not limit-
ed, enabling data transmission up to 16Mbps.
The MAX13430E–MAX13433E transceivers draw 2mA
of supply current when unloaded or when fully loaded
with
the
drivers
disabled.
The
MAX13430E/
MAX13431E are intended for half-duplex communica-
tions, and the MAX13432E/MAX13433E are intended
for full-duplex communications.
Low-Voltage Logic Interface
VL is the voltage supply for the low-voltage logic inter-
face and receiver output. VL operates with voltage sup-
ply from +1.62V to VCC.
Fail Safe
The MAX13430E family guarantees a logic-high receiv-
er output when the receiver inputs are shorted or open,
or when they are connected to a terminated transmis-
sion line with all drivers disabled. This is done by set-
ting the receiver input threshold between -50mV and
-200mV. If the differential receiver input voltage (A - B)
is greater than or equal to -50mV, RO is logic-high.
If (A - B) is less than or equal to -200mV, RO is logic-
low. In the case of a terminated bus with all transmitters
disabled, the receiver’s differential input voltage is
pulled to 0V by the termination. With the receiver
thresholds of the MAX13430E family, this results in a
logic-high with a 50mV minimum noise margin. The
-50mV to -200mV threshold complies with the ±200mV
EIA/TIA/RS-485 standard.
Hot-Swap Capability
When circuit boards are inserted into a hot or powered
backplane, differential disturbances to the data bus can
lead to data errors. Upon initial circuit-board insertion,
the data communication processor undergoes its own
power-up sequence. During this period, the processor’s
logic-output drivers are high impedance and are unable
to drive the DE and RE inputs of these devices to a
defined logic level. Leakage currents up to ±10A from
the high-impedance state of the processor’s logic drivers
could cause standard CMOS enable inputs of a trans-
ceiver to drift to an incorrect logic level. Additionally, par-
asitic circuit-board capacitance could cause coupling of
VL or GND to the enable inputs. Without the hot-swap
capability, these factors could improperly enable the
transceiver’s driver or receiver. When VL rises, an inter-
nal pulldown circuit holds DE low and RE high. After the
initial power-up sequence, the pulldown circuit becomes
transparent, resetting the hot-swap tolerable input.
±30kV ESD Protection
ESD-protection structures are incorporated on all pins
to protect against electrostatic discharges encoun-
tered during handling and assembly. The driver out-
puts and receiver inputs of the MAX13430E family of
devices have extra protection against static electricity.
Maxim’s engineers have developed state-of-the-
art structures to protect these pins against ESD of
±30kV without damage. The ESD structures withstand
high ESD in all states: normal operation, shutdown,
and powered down. After an ESD event, the
MAX13430E–MAX13433E keep working without latchup
or damage. ESD protection can be tested in various
ways. The transmitter outputs and receiver inputs of the
MAX13430E–MAX13433E are characterized for protec-
tion to the following limits:
±30kV using the Human Body Model
±10kV using the Contact Discharge method specified
in IEC 61000-4-2
±15kV using the Air Gap Discharge method specified
in IEC 61000-4-2
MAX13430E–MAX13433E
Maxim Integrated
15
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參數(shù)描述 |
|---|---|
| MAX1343BETX | 功能描述:ADC / DAC多通道 RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換速率: 分辨率:8 bit 接口類型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-40 |
| MAX1343BETX+ | 功能描述:ADC / DAC多通道 12-Bit 8Ch 300ksps 5.25V Precision ADC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換速率: 分辨率:8 bit 接口類型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-40 |
| MAX1343BETX+T | 功能描述:ADC / DAC多通道 12-Bit 8Ch 300ksps 5.25V Precision ADC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換速率: 分辨率:8 bit 接口類型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-40 |
| MAX1343BETX-T | 功能描述:ADC / DAC多通道 RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換速率: 分辨率:8 bit 接口類型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-40 |
| MAX13442EASA | 功能描述:RS-485接口IC RoHS:否 制造商:Texas Instruments 數(shù)據(jù)速率:250 Kbps 工作電源電壓:3.3 V 電源電流:750 uA 工作溫度范圍:- 40 C to + 125 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-8 封裝:Tube |
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