參數(shù)資料
型號: MAX1400CAI+T
廠商: Maxim Integrated Products
文件頁數(shù): 7/34頁
文件大小: 0K
描述: IC ADC 18BIT LP 28-SSOP
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 2,000
位數(shù): 18
采樣率(每秒): 480
數(shù)據(jù)接口: QSPI?,串行,SPI?
轉換器數(shù)目: 1
功率耗散(最大): 1.25mW
電壓電源: 模擬和數(shù)字
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 28-SSOP(0.209",5.30mm 寬)
供應商設備封裝: 28-SSOP
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 3 個差分,單極;3 個差分,雙極;5 個偽差分,單極;5 個偽差分,雙極
MAX1400
+5V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
______________________________________________________________________________________
15
channels, selection of either calibration mode (01 or 10)
will cause the scanning sequence to be extended to
include a conversion on both the CALGAIN+/
CALGAIN- input pair and the CALOFF+/CALOFF- input
pair. The exact sequence depends on the state of the
DIFF bit (Table 4). When scanning, the calibration
channels use the PGA gain, format, and DAC settings
defined by the contents of Transfer Function Register 3.
BUFF: (Default = 0) The BUFF bit controls operation of
the input buffer amplifiers. When this bit is 0, the inter-
nal buffers are bypassed and powered down. When
this bit is set high, the buffers drive the input sampling
capacitors and minimize the dynamic input load.
DIFF: (Default = 0) Differential/Pseudo-Differential Bit.
When DIFF = 0, the part is in pseudo-differential mode,
and AIN1–AIN5 are measured respective to AIN6, the
analog common. When DIFF = 1, the part is in differen-
tial mode with the analog inputs defined as AIN1/AIN2,
AIN3/AIN4, and AIN5/AIN6. The available input chan-
nels for each mode are tabulated in Table 5. Note that
DIFF also affects the scanning sequence when the part
is placed in SCAN mode (Table 4).
BOUT: (Default = 0) Burnout Current Bit. Setting BOUT
= 1 connects 100nA current sources to the selected
analog input channel. This mode is used to check that
a transducer has not burned out or opened circuit. The
burnout current source must be turned off (BOUT = 0)
before measurement to ensure best linearity.
RESERVED: (Default = 0) Reserved Bit. A 0 must be
written to this location.
X2CLK: (Default = 0) Times-Two Clock Bit. Setting this
bit to 1 selects a divide-by-2 prescaler in the clock sig-
nal path. This allows use of a higher frequency crystal
or clock source and improves immunity to asymmetric
clock sources.
Table 2. Data Output Rate vs. CLK, Filter Select, and Modulator Frequency Bits
*Data rates offering noise-free 16-bit resolution.
Note: When FAST = 0, f-3dB = 0.262 Data Rate. When FAST = 1, f-3dB = 0.443 Data Rate.
Default condition is in bold print.
Table 3. Special Modes Controlled by M1, M0 (SCAN = 0)
DESCRIPTION
M1
0
1
Normal Mode: The device operates normally.
Calibrate Gain: In this mode the MAX1400 converts the voltage applied across CALGAIN+
and CALGAIN-. The PGA gain, DAC, and format settings of the selected channel (defined by
DIFF, A1, A0) are used.
1
Reserved: Do not use.
1
0
Calibrate Offset: In this mode the MAX1400 converts the voltage applied across CALOFF+
and CALOFF-. The PGA gain, DAC, and format settings of the selected channel (defined by
DIFF, A1, A0) are used.
1
M0
0
1.024
CLKIN
FREQ.
2.048
X2CLK = 1
fCLKIN
(MHz)
CLKIN
FREQ.
25
20
FS1, FS0
(0, 1)
(sps)*
200
X2CLK = 0
fCLKIN
(MHz)
AVAILABLE OUTPUT DATA RATES
100
FS1, FS0
(0, 0)
(sps)*
FS1, FS0
(1, 1)
(sps)
FS1, FS0
(1, 0)
(sps)
1.024
2.048
50
40
400
200
1.024
2.048
100
80
800
400
1.024
2.048
200
160
1600
800
2.4576
4.9152
60
50
600
300
2.4576
4.9152
120
100
1200
600
2.4576
4.9152
240
200
2400
1200
2.4576
4.9152
480
400
4800
2400
CLK
0
1
1
MF1
0
1
0
0
1
MF0
0
1
0
1
0
1
0
1
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