參數(shù)資料
型號: MAX1400EAI+T
廠商: Maxim Integrated Products
文件頁數(shù): 11/34頁
文件大小: 0K
描述: IC ADC 18BIT LP 28-SSOP
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 2,000
位數(shù): 18
采樣率(每秒): 480
數(shù)據(jù)接口: QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 1.25mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 28-SSOP(0.209",5.30mm 寬)
供應商設備封裝: 28-SSOP
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 3 個差分,單極;3 個差分,雙極;5 個偽差分,單極;5 個偽差分,雙極
MAX1400
+5V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
______________________________________________________________________________________
19
Table 10. Transfer-Function Register Mapping—Gain-Cal Mode (M1 = 1, M0 = 0)
X = Don’t Care.
First Bit (Data MSB)
RESERVED BITS
CHANNEL ID TAG
D1
‘0’
D0
‘0’
CID0
DATA BITS
CID2
CID1
D9
D5
D8
D7
D6
D2
DATA BITS
D4
D3
(Data LSB)
(LSB)
D17
D13
D16
D15
D14
D10
DATA BITS
D12
D11
0
DIFF
0
A1
0
1
0
1
0
1
2
0
2
1
0
X
0
X
1
0
X
0
X
2
1
2
1
0
1
0
2
SCAN
0
1
TRANSFER
FUNCTION REG.
1
X
1
X
3
1
0
X
0
X
3
1
0
X
1
X
1
3
1
0
A0
1
0
1
X
0
1
0
3
X
CALGAIN+–CALGAIN-
AIN2–AIN6
AIN4–AIN6
AIN3–AIN6
AIN1–AIN6
CALGAIN+–CALGAIN-
CHANNEL
1
CALGAIN+–CALGAIN-
CALOFF+–CALOFF-
AIN1–AIN2
CALGAIN+–CALGAIN-
AIN5–AIN6
1
X
1
X
3
1
3
2
1
X
AIN5–AIN6
CALGAIN+–CALGAIN-
CALOFF+–CALOFF-
AIN3–AIN4
1
Do not use
0
1
Do not use
1
Data Register (Read-Only)
The data register is a 24-bit, read-only register. Any
attempt to write data to this location will have no effect.
If a write operation is attempted, 8 bits of data must be
clocked into the part before it will return to its normal
idle mode, expecting a write to the communications
register.
Data is output MSB first, followed by three reserved 0
bits and a 3-bit channel ID tag indicating the channel
from which the data originated.
D17–D0: The conversion result. D17 is the MSB. The
result is in offset binary format. 00 0000 0000 0000
0000 represents the minimum value and 11 1111 1111
1111 1111 represents the maximum value. Inputs
exceeding the available input range are limited to the
corresponding minimum or maximum output values.
0: These reserved bits will always be 0.
CID2–0: Channel ID tag (Table 11).
Data Register (Read-Only) Bits
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