參數(shù)資料
型號： MAX1403CAI+T
廠商： Maxim Integrated Products
文件頁數(shù)： 11/36頁
文件大?。?/td> 0K
描述： IC ADC 18BIT LP 28-SSOP
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準包裝： 2,000
位數(shù)： 18
采樣率（每秒）： 480
數(shù)據(jù)接口： QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 21.45mW
電壓電源： 模擬和數(shù)字
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 28-SSOP（0.209"，5.30mm 寬）
供應(yīng)商設(shè)備封裝： 28-SSOP
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 3 個差分，單極；3 個差分，雙極；5 個偽差分，單極；5 個偽差分，雙極
MAX1403
+3V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
______________________________________________________________________________________
19
Analog Inputs AIN1 to AIN6
Inputs AIN1 and AIN2 map to transfer-function register
1, regardless of scanning mode (SCAN = 1) or single-
ended vs. differential (DIFF) modes. Likewise, AIN3 and
AIN4 inputs always map to transfer-function register 2.
Finally, AIN5 always maps to transfer-function register 3
(input AIN6 is analog common).
CALGAIN and CALOFF
When not in scan mode (SCAN = 0), A1 and A0 select
which transfer function applies to CALGAIN and
CALOFF. In scan mode (SCAN = 1), CALGAIN and
CALOFF are always mapped to transfer-function regis-
ter 3. Note that when scanning while M1
≠ M0, the scan
sequence includes both CALGAIN and CALOFF chan-
nels (Table 4). CALOFF always precedes CALGAIN,
even though both channels share the same channel ID
tag (Table 11).
Note that changing the status of any active channel
control bits will cause INT to immediately transition high
and the modulator/filter to be reset. INT will reassert
after the appropriate digital-filter settling time. The con-
trol settings of the inactive channels may be changed
freely without affecting the status of INT or causing the
filter/modulator to be reset.
PGA Gain
Bits G2–G0 control the PGA gain according to Table 6.
Unipolar/Bipolar Mode
The U/B bit places the channel in either bipolar or
unipolar mode. A 0 selects bipolar mode, and a 1
selects unipolar mode. This bit does not affect the ana-
log-signal conditioning. The modulator always accepts
bipolar inputs and produces a bitstream with 50%
ones-density when the selected inputs are at the same
potential. This bit controls the processing of the digital-
filter output, such that the available output bits are
mapped to the correct output range. Note that U/B
must be set before a conversion is performed; it will not
affect any data already held in the output register.
Selecting bipolar mode does not imply that any input
may be taken below AGND. It simply changes the gain
and offset of the part. All inputs must remain within their
specified operating voltage range.
Offset-Correction DACs
Bits D3–D0 control the offset-correction DAC. The DAC
range depends on the PGA gain setting and is
expressed as a percentage of the available full-scale
input range (Table 7).
D3 is a sign bit, and D2–D0 represent the DAC magni-
tude. Note that when a DAC value of 0000 is pro-
grammed (the default), the DAC is disconnected from
the modulator inputs. This prevents the DAC from
degrading noise performance when offset correction is
not required.
Transfer-Function Register Mapping
Tables 8, 9, and 10 show the channel-control register
mapping in the various operating modes.
Table 6. PGA Gain Codes
Table 7. DAC Code vs. DAC Value
0
G1
0
G0
0
1
x2
0
1
0
1
x8
0
x4
x1
0
1
x32
1
0
1
x128
1
x64
x16
1
G2
PGA GAIN
-66.7
-100
-116.7
-83.3
+66.7
+100
+116.7
UNIPOLAR
DAC VALUE
(% of FSR)
+83.3
DAC not connected
-33.3
-50
-16.7
DAC not connected
+33.3
+50
+16.7
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
D0
0
1
-33.3
-50
1
-58.3
1
-41.6
0
1
0
1
0
+33.3
+50
0
+58.3
1
0
+41.6
0
1
0
1
BIPOLAR
DAC VALUE
(% of FSR)
D3
1
-16.7
1
-25
1
0
1
0
1
-8.3
0
+16.7
0
+25
1
0
1
0
+8.3
0
D1
0
D2
0
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