參數(shù)資料
型號(hào)： MAX1426EAI+
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 3/16頁(yè)
文件大?。?/td> 0K
描述： IC ADC 10BITS 10MSPS 28SSOP
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 46
位數(shù)： 10
采樣率（每秒）： 10M
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 210mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 28-SSOP（0.209"，5.30mm 寬）
供應(yīng)商設(shè)備封裝： 28-SSOP
包裝： 管件
輸入數(shù)目和類型： 1 個(gè)差分，雙極
MAX1426
10-Bit, 10Msps ADC
______________________________________________________________________________________
11
and REFN. In this mode, the voltages at these pins
are set to their nominal values (see
Electrical
Characteristics). The reference voltage levels can be
adjusted externally by applying a voltage at REFIN.
This allows other input levels to be used as well. The
full external reference mode is entered when REFIN =
AGND. External voltages can be applied to REFP,
CML, and REFIN. In this mode, the internal voltage
shuts down, resulting in less overall power consump-
tion.
Clock Input (CLK)
CLK is TTL/CMOS compatible. Since the interstage
conversion of the device depends on the rising and
falling edges of the external clock, use a clock with low
jitter and fast rise and fall times (<2ns). Low clock jitter
improves SNR performance. The MAX1426 operates
with a 50% duty cycle. If the clock has a duty cycle
other than 50%, the clock must meet the specifications
for high and low periods as stated in the
Electrical
Characteristics.
Output Enable/Power-Down Function
(
OE//PD) and Output Data
All data outputs, D0 through D9, are TTL/CMOS-logic
compatible. There is a 5.5 clock-cycle latency between
the start convert signal and the valid output data. The
output coding for the MAX1426 is in binary two’s com-
plement format, which has the MSB inverted (Table 1).
The digital output goes into a high-impedance state
and the device into a low-power mode when OE/PD
goes high. For normal operation, drive OE low. The out-
puts are not designed to drive high capacitances or
n - 6
n
n - 5
n + 1
n - 4
n + 2
n - 3
n + 3
n - 2
n + 4
n - 1
n + 5
n
n + 6
n + 1
n + 7
5.5 CLOCK-CYCLE LATENCY
ANALOG INPUT
CLOCK INPUT
DATA OUTPUT
Figure 3. System Timing Diagram
Figure 4. Output Timing Diagram
DATA 0
INPUT
CLK
OUTPUT
DATA
tOD
tCLK
tCH
tCI
DATA 1
DATA 2
1 1 1 1 1 1 1 1 1 1
-1 LSB
1 1 1 0 0 0 0 0 0 0
-1/4 Full Scale
1 1 0 0 0 0 0 0 0 0
-1/2 Full Scale
0 1 0 0 0 0 0 0 0 0
+1/2 Full Scale
0 0 1 0 0 0 0 0 0 0
+1/4 Full Scale
0 0 0 0 0 0 0 0 0 1
+1 LSB
0 0 0 0 0 0 0 0 0 0
Bipolar Zero
0 1 1 0 0 0 0 0 0 0
+3/4 Full Scale
0 1 1 1 1 1 1 1 0 1
+Full Scale 2LSB
0 1 1 1 1 1 1 1 1 0
+Full Scale 1LSB
0 1 1 1 1 1 1 1 1 1
+Full Scale
OUTPUT CODE
(TWO’S COMPLEMENT)
DIFFERENTIAL INPUT
Table 1. MAX1426 Output Code
1 0 1 0 0 0 0 0 0 0
-3/4 Full Scale
1 0 0 0 0 0 0 0 0 1
-Full Scale + 1LSB
1 0 0 0 0 0 0 0 0 0
-Full Scale
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