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參數(shù)資料
| 型號： | MAX1434ECQ+TD |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 4/22頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 10BIT 50MSPS 100-TQFP |
| 標準包裝： | 500 |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 50M |
| 數(shù)據(jù)接口： | LVDS，串行 |
| 轉(zhuǎn)換器數(shù)目： | 8 |
| 功率耗散（最大）： | 882mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | * |
| 封裝/外殼： | 100-TQFP 裸露焊盤 |
| 供應商設備封裝： | 100-TQFP（14x14） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 8 個差分 |
MAX1434
Detailed Description
The MAX1434 ADC features fully differential inputs, a
pipelined architecture, and digital error correction for
high-speed signal conversion. The ADC pipeline archi-
tecture moves the samples taken at the inputs through
the pipeline stages every half clock cycle. The convert-
ed digital results are serialized and sent through the
LVDS/SLVS output drivers. The total clock-cycle latency
from input to output is 6.5 clock cycles.
The MAX1434 offers eight separate fully differential chan-
nels with synchronized inputs and outputs. Configure the
outputs for binary or two’s complement with the T/B digital
input. Global power-down minimizes power consumption.
Input Circuit
Figure 1 displays a simplified diagram of the input T/H
circuits. In track mode, switches S1, S2a, S2b, S4a, S4b,
S5a, and S5b are closed. The fully differential circuits
sample the input signals onto the two capacitors (C2a
and C2b) through switches S4a and S4b. S2a and S2b
set the common mode for the operational transconduc-
tance amplifier (OTA), and open simultaneously with S1,
sampling the input waveform. Switches S4a, S4b, S5a,
and S5b are then opened before switches S3a and S3b
connect capacitors C1a and C1b to the output of the
amplifier and switch S4c is closed. The resulting differ-
ential voltages are held on capacitors C2a and C2b. The
amplifiers charge capacitors C1a and C1b to the same
values originally held on C2a and C2b. These values are
Octal, 10-Bit, 50Msps, 1.8V ADC
with Serial LVDS Outputs
12
______________________________________________________________________________________
LVDS/SLVS
OUTPUT
DRIVERS
PLL
5x
CLOCK
CIRCUITRY
REFERENCE SYSTEM
IN0P
IN0N
IN1P
IN1N
IN7P
IN7N
CLK
REFADJ REFIO REFP REFN
OUT0P
OUT0N
OUT1P
OUT1N
OUT7P
OUT7N
OVDD
AVDD
GND
CVDD
PLL3
PLL1
PLL2
LVDSTEST
DT
OUTPUT
CONTROL
MAX1434
T/H
10-BIT
PIPELINE
ADC
10:1
SERIALIZER
T/H
10-BIT
PIPELINE
ADC
10:1
SERIALIZER
FRAMEP
FRAMEN
CLKOUTP
CLKOUTN
T/H
10-BIT
PIPELINE
ADC
10:1
SERIALIZER
POWER
CONTROL
PD
SLVS/LVDS
T/B
*ICMV = INPUT COMMON-MODE VOLTAGE (INTERNALLY GENERATED).
CMOUT
ICMV*
Functional Diagram
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