參數資料
型號: MAX14502AETL+
廠商: Maxim Integrated Products
文件頁數: 17/41頁
文件大?。?/td> 0K
描述: IC CARD READER USB-SD 40-TQFN
產品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 60
應用: USB
接口: I²C,2 線串口
電源電壓: 1.8 V ~ 3.3 V
封裝/外殼: 40-WFQFN 裸露焊盤
供應商設備封裝: 40-TQFN-EP(5x5)
包裝: 管件
安裝類型: 表面貼裝
MAX14500–MAX14503
Hi-Speed USB-to-SD Card
Readers with Bypass
24
______________________________________________________________________________________
grammed to stay asserted until the status register is
read, or stay asserted for 10ms. If INT is programmed to
stay asserted, a read to the status register is required to
clear INT. INT can be programmed to be active-high or
active-low when I2C_SEL is high (I2C control). INT is
high impedance in Sleep mode (WAKEUP = 0), regard-
less of the INT polarity programmed in the I2C registers.
Use a pullup or pulldown resistor for the desired inactive
INT polarity state during Sleep mode.
Interrupt Masking
All interrupts are masked at power-up. While masked
interrupts do not assert the INT output, they do register
as changes in the interrupt request registers (IRQ1 and
IRQ2). The status register (STATUS1 = 0x12) indicates
the current state of the interrupt bits. If interrupts are
masked, polling IRQ1 and IRQ2 indicate the fields with
changes, and STATUS1 gives the current state.
Reading the IRQ registers resets the interrupt request
bits. If polling is used to read the device status, it is
required to read both the status register and the inter-
rupt request registers to check for state changes.
USB Interrupts
When enabled, the INT output asserts an interrupt for
changes in the USB connection and if the operating
system suspends the USB connection. VBUS is detect-
ed at the KVBUS input and changes in VBUS voltage
can assert an interrupt when enabled.
Power-Supply Interrupts
The MAX14500–MAX14503 feature many advanced
power-saving modes. VCC, VSD, and VTM do not need to
be applied for I2C communication. Changes in VSD and
VTM can assert an interrupt when enabled to indicate dif-
ferent power-saving modes (see the
Power-Supply
Modes section).
Busy Interrupt
When enabled, changes in the BSY bit can assert an
interrupt (see the
Busy Indication (BSY) section).
SD Status Interrupt
When enabled, the SDSTAT bit asserts an interrupt for
card detection and removal upon entering Card Reader
mode for the SD card socket configured as the card
reader. The SDSTAT bit is not active during Pass Thru
mode and does not change states in the IRQ registers
upon card insertion and removal during Pass Thru mode.
BIT
DESCRIPTION
VALUE
FUNCTION
DEFAULT
[7:5]
RESERVED
000
Set these bits to 0.
000
0
Analog switches are open,
disconnecting the SD port
from the SD card.
4
SD PORT 2 ANALOG SWITCHES
SD Port 2 is a set of six analog switches connecting the SD port to the
SD card. This set contains: clock (CCLK2), command (CCMD2), and
four data lines (CDAT2_[3:0]). The card-present line is not available
for this port. This setting is ignored when Card Reader mode is
enabled for this port.
1
Analog switches are
closed, connecting the SD
port to the SD card.
1
0
Analog switches are open,
disconnecting the SD port
from the SD card.
3
SD PORT 1 ANALOG SWITCHES
SD Port 1 is a set of seven analog switches connecting the SD port to
the SD card. This set contains: card-present (CCRD_PRST), clock
(CCLK1), command (CCMD1), and four data lines (CDAT1_[3:0]). The
difference between Port 1 and Port 2 is the card-present line. This
setting is ignored when Card Reader mode is enabled for this port.
1
Analog switches are
closed, connecting the SD
port to the SD card.
1
00, 11
Card Reader mode not
active.
01
Card Reader mode active:
Connects to SD card 1.
[2:1]
CARD READER MODE
Changing these bits in Sleep mode does not execute the action until
the host P wakes up the MAX14500–MAX14503.
10
Card Reader mode active:
Connects to SD card 2.
00
0
Request internal logic to
shut down.
0
WAKEUP
In Sleep mode, the MAX14500–MAX14503 are in Pass Thru mode. SD
port switches are controlled by their respective bits. Entering Sleep
mode reduces the supply current by turning off the internal logic.
Request to shut down may be delayed due to USB and de-
enumeration.
1
Wake up internal logic.
0
Table 2. Control Register (0x00)
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