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參數(shù)資料
| 型號(hào)： | MAX14582EWC+T |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 8/21頁(yè) |
| 文件大小： | 0K |
| 描述： | IC TXRX USB 2.0 FS 5WIRE 12WLP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | * |
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Industry’s Smallest and Lowest (VL) Full-Speed
USB Transceivers, with Low VIO 3/5-Wire Interface
MAX14581/MAX14582
16
VTRM
An internal linear regulator generates the VTRM voltage
(+3.3V typ). VTRM derives power from VBUS (see the
internal USB circuitry and provides the pullup voltage for
the internal 1.5kI resistor. Bypass VTRM to GND with a
1FF ceramic capacitor as close as possible to the device.
Do not use VTRM to provide power to external circuitry.
RCV (MAX14582)
RCV is the output of the differential USB receiver. RCV is
a logic-high for D+ high and D- low. RCV is a logic-low
for D+ low and D- high. RCV retains the last valid logic
state when D+ and D- are both low (SE0). RCV is driven
BD (MAX14581)
The VBUS detect (BD) output is asserted high when a
voltage greater than VTH-BUS is presented on VBUS. This
is typically the case when the MAX14581 is connected to
a powered USB. BD is low when VBUS is unconnected.
The MAX14582 doesn’t have the BD pin. Nevertheless,
the status of VBUS is provided by encoding VP and VM
as follows: VP = VM = high.
Applications Information
External Capacitors
Use three external capacitors for proper operation.
Bypass VL to GND with a 0.1FF ceramic capacitor.
Bypass VBUS to GND with a 1FF ceramic capacitor.
Bypass VTRM to GND with a 1FF (min) ceramic or plastic
capacitor. Place all capacitors as close as possible to
the device.
USB Data Transfer
Transmitting Data, 3 Wires (MAX14581)
The MAX14581 transmit USB data to the USB differential-
ly on D+ and D- when OE is low. The D+ and D- outputs
are determined by SE0 and DAT (see Table 3).
Receiving Data, 3 Wires (MAX14581)
Drive OE high and SUS low to receive data on D+/D-.
Differential data received on D+ and D- appears at DAT.
SE0 goes high only when both D+ and D- are low
Table 3. Transmit Truth Table, 3 Wires
Table 4a. Receive Truth Table, 3 Wires,
SUS = 0
Table 4b. Receive Truth Table, 3 Wires,
SUS = 1
*Last state.
**D+/D- differential receiver output.
X = Undefined
*D+ single-ended receiver output.
(OE = 0)
INPUTS
OUTPUTS
DAT
SE0
D+
D-
0
1
0
1
0
1
0
1
0
1
0
(OE = 1, SUS = 0)
INPUTS
OUTPUTS
D+
D-
DAT
SE0
0
*DAT
1
0
1
**0
0
1
0
**1
0
1
X
0
(OE = 1, SUS = 1)
INPUTS
OUTPUTS
D+
D-
DAT
SE0
0
1
0
1
0
1
0
*1
0
1
*1
0
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