參數(shù)資料
型號(hào): MAX147BEPP+
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 13/24頁(yè)
文件大小: 0K
描述: IC ADC 12BIT SERIAL 20-DIP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 18
位數(shù): 12
采樣率(每秒): 133k
數(shù)據(jù)接口: MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 889mW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 通孔
封裝/外殼: 20-DIP(0.300",7.62mm)
供應(yīng)商設(shè)備封裝: 20-PDIP
包裝: 管件
輸入數(shù)目和類(lèi)型: 8 個(gè)單端,單極;8 個(gè)單端,雙極;4 個(gè)差分,單極;4 個(gè)差分,雙極
MAX146/MAX147
+2.7V, Low-Power, 8-Channel,
Serial 12-Bit ADCs
20
______________________________________________________________________________________
VREF, the DC input resistance is a minimum of 18k
.
During conversion, an external reference at VREF must
deliver up to 350A DC load current and have 10
or
less output impedance. If the reference has a higher
output impedance or is noisy, bypass it close to the
VREF pin with a 4.7F capacitor.
Using the REFADJ input makes buffering the external
reference unnecessary. To use the direct VREF input,
disable the internal buffer by tying REFADJ to VDD. In
power-down, the input bias current to REFADJ is typi-
cally 25A (MAX146) with REFADJ tied to VDD. Pull
REFADJ to AGND to minimize the input bias current in
power-down.
Transfer Function
Table 7 shows the full-scale voltage ranges for unipolar
and bipolar modes.
The external reference must have a temperature coeffi-
cient of 4ppm/°C or less to achieve accuracy to within
1LSB over the 0°C to +70°C commercial temperature
range.
Figure 17 depicts the nominal, unipolar input/output
(I/O) transfer function, and Figure 18 shows the bipolar
input/output transfer function. Code transitions occur
halfway between successive-integer LSB values.
Output coding is binary, with 1LSB = 610V (2.500V /
4096) for unipolar operation, and 1LSB = 610V
[(2.500V / 2 - -2.500V / 2) / 4096] for bipolar operation.
Layout, Grounding, and Bypassing
For best performance, use printed circuit boards.
Wire-wrap boards are not recommended. Board layout
should ensure that digital and analog signal lines are
separated from each other. Do not run analog and digi-
tal (especially clock) lines parallel to one another, or
digital lines underneath the ADC package.
Figure 19 shows the recommended system ground
connections. Establish a single-point analog ground
(star ground point) at AGND, separate from the logic
ground. Connect all other analog grounds and DGND
to the star ground. No other digital system ground
should be connected to this ground. For lowest-noise
operation, the ground return to the star ground’s power
supply should be low impedance and as short as
possible.
High-frequency noise in the VDD power supply may
affect the high-speed comparator in the ADC. Bypass
the supply to the star ground with 0.1F and 1F
capacitors close to pin 20 of the MAX146/MAX147.
Minimize capacitor lead lengths for best supply-noise
rejection. If the power supply is very noisy, a 10
resis-
tor can be connected as a lowpass filter (Figure 19).
High-Speed Digital Interfacing with QSPI
The MAX146/MAX147 can interface with QSPI using
the circuit in Figure 20 (fSCLK = 2.0MHz, CPOL = 0,
CPHA = 0). This QSPI circuit can be programmed to do a
conversion on each of the eight channels. The result is
stored in memory without taxing the CPU, since QSPI
incorporates its own microsequencer.
The MAX146/MAX147 are QSPI compatible up to the
maximum external clock frequency of 2MHz.
OUTPUT CODE
FULL-SCALE
TRANSITION
11 . . . 111
11 . . . 110
11 . . . 101
00 . . . 011
00 . . . 010
00 . . . 001
00 . . . 000
12
3
0
(COM)
FS
FS - 3/2LSB
FS = VREF + COM
ZS = COM
INPUT VOLTAGE (LSB)
1LSB =
VREF
4096
Figure 17. Unipolar Transfer Function, Full Scale (FS) = VREF
+ COM, Zero Scale (ZS) = COM
UNIPOLAR MODE
BIPOLAR MODE
Full Scale
Zero Scale
Positive
Zero
Negative
Full Scale
Scale
Full Scale
VREF + COM
COM
VREF / 2
COM
-VREF / 2
+ COM
Table 7. Full Scale and Zero Scale
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