15
MAX14824
IO-Link Master Transceiver
Pin Description (continued)
Detailed Description
The MAX14824 is an IO-LinkM master transceiver that
integrates an IO-Link physical interface with an additional
24V digital input and two LDOs. A 12MHz SPIK interface
allows fast programming and monitoring.
The device supports COM1, COM2, and COM3 IO-Link
data rates and has the option of limiting emitted EMI by
selecting a lower slew rate at lower data rates. The auto-
matic wake-up circuitry determines the correct wake-up
pulse polarity, allowing the use of simple UARTs for
wake-up pulse generation.
The C/Q and DI inputs have selectable current sinks that
can be enabled for use in actuators.
The device is configured and monitored through an SPI
interface. Extensive alarms are available through SPI.
24V Interface
The device features an IO-Link transceiver interface
capable of operating with voltages up to 36V. This
includes the C/Q input/output and the logic-level digital
input (DI).
DI is reverse-polarity protected. Short-circuit protection is
provided on the C/Q driver.
Configurable C/Q Driver
The device’s C/Q driver has a selectable push-pull, high-
side (PNP), or low-side (NPN) switching driver.
Set the C/Q_N/P and C/Q_PP bits in the CQConfig reg-
ister to select the driver mode for the C/Q driver. When
configured as a push-pull output, C/Q switches between
VCC and ground. Set the C/Q_PP bit to 1 to select push-
pull operation. Set the C/Q_PP bit to 0 to configure the
C/Q output for open-drain operation. The C/Q_N/P bit
selects NPN or PNP operation when C/Q is configured as
an open-drain output.
C/Q Driver and Receiver
The C/Q driver can be enabled through hardware
(TXEN) or software (C/QDEn). Drive TXEN high to
enable the C/Q driver and drive TXEN low to disable
the driver. The C/Q driver can be enabled through the
C/QDEn bit in the C/QConfig register.
The C/Q driver on the device is specified for 300mA
to drive large capacitive loads over 1FF and dynamic
impedances like incandescent lamps.
IO-Link is a registered trademark of Procibus User
Organization (PNO).
SPI is a trademark of Motorola Inc.
PIN
NAME
FUNCTION
14
RX
Receiver Output. RX is the inverse logic level of C/Q. RX is always high when the RxDis bit in the
CQConfig register is set to 1.
15
WUEN
Wake-Up Enable Input. Drive WUEN high to enable automatic wake-up pulse generation.
16
A2
Chip-Select Address Input 2. Do not leave A2 unconnected.
17
LI
Logic Output of 24V DI Logic Input. LI is the inverse logic of DI. LI is referenced to VL.
18
UV
Open-Drain Undervoltage Indicator Output. UV is active high.
19
DI
24V Logic-Level Digital Input
20
GND
Ground
21
C/Q
SIO/IO-Link Data Input/Output. Drive TXEN high to enable the C/Q driver. The logic on the C/Q output is
the inverse logic level of the signals on the TXC and TXQ inputs. Drive TXEN low to disable the C/Q
driver. RX is the logic inverse of C/Q.
22
A1
Chip-Select Address Input 1. Do not leave A1 unconnected.
23
VCC
Power-Supply Input. Bypass VCC to GND with a 1FF ceramic capacitor.
24
A0
Chip-Select Address Input 0. Do not leave A0 unconnected.
—
EP
Exposed Pad. Connect EP to GND.