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參數(shù)資料
| 型號(hào)： | MAX14830ETM+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 54/68頁 |
| 文件大?。?/td> | 0K |
| 描述： | SEMICONDUCTOR OTHER |
| 標(biāo)準(zhǔn)包裝： | 43 |
| 系列： | * |
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58
Maxim Integrated
Quad Serial UART with 128-Word FIFOs
MAX14830
Serial Controller Interface
The MAX14830 can be controlled through SPI or I2C as
defined by the logic on SPI/I2C. See the Pin Configuration
section for further details.
SPI Interface
The SPI interface supports both single cycle and burst
read/write access. The SPI master must generate clock
and data signals in SPI MODE0 (i.e. with clock polarity
CPOL = 0 and clock phase CPHA = 0).
Each of the four UARTs is addressed using 2 bits (U1
and U0) in the command byte (see Tables 10 and 11).
MISO Operation
Before a specific UART has been addressed, all four
UARTs can attempt to drive MISO. To avoid this conten-
tion, the MISO line is held in high impedance during a
write cycle (Figure 18).
During a read cycle, MISO is high impedance for the
first 4 clock cycles of the command byte. Once the SPI
address (U1 and U0) has been properly decoded, the
addressed SPI drives the MISO line (Figure 19).
SPI Burst Access
Burst access allows writing and reading in one block,
by only defining the initial register address in the SPI
command byte. Multiple characters can be loaded into
the TxFIFO by using the THR (0x00) as the initial burst
write address. Similarly, multiple characters can be read
out of the RxFIFO by using the RHR (0x00) as the SPI’s
burst read address. If the SPI burst address is differ-
ent to 0x00, the MAX14830 automatically increments
the register address after each SPI data byte. Efficient
programming of multiple consecutive registers is thus
possible. Chip select, CS/A0, must be kept low during
the whole cycle. The SCLK/SCL clock continues clocking
throughout the burst access cycle. The burst cycle ends
when the SPI master pulls CS/A0 high.
For example, writing 128 bytes into a TxFIFO can be
achieved by a burst write access through the following
sequence:
1) Pull CS/A0 low.
2) Send SPI write command.
3) Send 128 bytes.
4) Release CS/A0.
This takes a total of (1 + 128) x 8 clock cycles.
Table 10. SPI Command Byte Configuration
A[4:0] = Register Address
Figure 18. SPI Write Cycle
Table 11. SPI U1, U0 UART Selection
SCLK
MOSI
MISO
X
CS
AX = REGISTER ADDRESS
UX = UART ADDRESS
DX = EIGHT-BIT REGISTER CONTENTS
= INSTANT AT WHICH MAX14830 SAMPLES MOSI DATA
WU1U0A4A3A2A1A0D7D6D5D4D3D2D1D0
HiZ
SPI COMMAND BYTE
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
W/R
U1
U0
A4
A3
A2
A1
A0
U1
U0
UART SELECTED
0
UART0
0
1
UART1
1
0
UART2
1
UART3
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX14830ETM+ | 功能描述:UART 接口集成電路 Quad Serial UART w/128-Word FIFOs RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| MAX14830ETM+T | 功能描述:UART 接口集成電路 Quad Serial UART w/128-Word FIFOs RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| MAX14830EVKIT# | 功能描述:界面開發(fā)工具 MAX14830 Eval Kit RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評(píng)估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| MAX14830EVKIT+ | 制造商:Maxim Integrated Products 功能描述:QUAD UART EV-KIT WITH IO-LINK AND MULTIPROTOCOL - Boxed Product (Development Kits) |
| MAX1483C/D+ | 功能描述:RS-485接口IC low-power transceivers for RS-485 and RS-422 communication RoHS:否 制造商:Texas Instruments 數(shù)據(jù)速率:250 Kbps 工作電源電壓:3.3 V 電源電流:750 uA 工作溫度范圍:- 40 C to + 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 封裝:Tube |
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