參數(shù)資料
型號(hào): MAX1513ETP
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類(lèi): 穩(wěn)壓器
英文描述: TFT-LCD Power-Supply Controllers
中文描述: SWITCHING CONTROLLER, 1725 kHz SWITCHING FREQ-MAX, PQCC20
封裝: 4 X 4 MM, 0.80 MM HEIGHT, MO-220-VGGD, TQFN-20
文件頁(yè)數(shù): 21/28頁(yè)
文件大?。?/td> 540K
代理商: MAX1513ETP
M
TFT-LCD Power-Supply Controllers
______________________________________________________________________________________
21
In the circuits of Figures 1 and 2, the maximum total
voltage ripple is 1% (peak-to-peak) of the 15V output,
which corresponds to 150mV peak-to-peak ripple. A
conservative way to calculate the maximum ESR and
minimum capacitance is to assume the ESR ripple and
the capacitive ripple each should not exceed 50% of
the total ripple budget.
where V
RIPPLE(MAX)
is the total peak-to-peak output rip-
ple. Since the peak inductor current calculated in the
Inductor Selection
section is 2.6A, the maximum ESR of
the output capacitor should be less than 29m
. On the
other hand, only 3.1μF capacitance is needed to meet
the capacitive ripple requirement based on the calcula-
tion. A 10μF AQU-series POSCAP with maximum ESR
of 20m
is selected for the typical operating circuits in
Figures 1 and 2, which meets both the voltage-ripple
and minimum capacitance requirements.
The typical load on the step-up regulator for source-
driver applications is a large pulsed load, with a peak
current of approximately 1A and a pulse width of
approximately 2μs. The shape of the pulse is close to
triangular, so it is equivalent to a square pulse with 1A
height and 1μs pulse width. The total voltage dip during
the pulsed load transient also has two components: the
ohmic dip due to the output capacitor’s ESR and the
capacitive dip caused by discharging the output
capacitance:
where I
PULSE
is the height of the pulse load and t
PULSE
is the pulse width. Higher capacitance and lower ESR
result in less voltage dip. Again, assume the ESR dip
and the capacitive dip each should not exceed 50% of
the total maximum allowed output-voltage dip caused
by a load pulse (V
DIP(MAX)
).
For the typical load pulse described above, assuming the
voltage dip must be limited to 200mV, the minimum out-
put capacitor is 10μF, and the maximum ESR is 100m
.
The voltage rating and temperature characteristics of
the output capacitor must also be considered.
Input-Capacitor Selection
The input capacitor (C
IN
) reduces the current peaks
drawn from the input supply and reduces noise injec-
tion into the device. A 22μF ceramic capacitor is used
in the typical operating circuit (Figure 1) because of the
high source impedance seen in typical lab setups.
Actual applications usually have much lower source
impedance since the step-up regulator often runs
directly from the output of another regulated supply.
Typically, C
IN
can be reduced below the values used in
the typical operating circuit. Ensure a low noise supply
at IN by using adequate C
IN
. Alternately, greater volt-
age variation can be tolerated on C
IN
if IN is decoupled
from C
IN
using an RC lowpass filter (see R11 and C10
in Figure 1).
Rectifier Diode
The MAX1513/MAX1514s’ high switching frequency
demands a high-speed rectifier. Schottky diodes are
recommended for most applications because of their
fast recovery time and low forward voltage. In general,
use a Schottky diode with a current rating exceeding
the peak inductor current calculated in the
Inductor
Selection
section.
Output-Voltage Selection
The output voltage of the main step-up regulator is
adjustable by connecting a resistive voltage-divider
from the output (V
MAIN
) to the analog ground plane
with the center tap connected to FB (see Figure 1).
Select R2 in the 10k
to 50k
range. Calculate R1 with
the following equations:
where V
FB
, the step-up regulator’s feedback set point,
is 1.25V. Connect the divider close to the IC.
Output-Capacitor Stability Requirement
The step-up regulator controller of the MAX1513/
MAX1514 uses a peak current-mode control method.
The loop stability of a current-mode step-up regulator
can be analyzed using a small-signal model. In contin-
uous-conduction mode, the loop-gain transfer function
consists of a DC loop gain, a dominant pole, a right-
half-plane (RHP) zero and an ESR zero.
R
R
V
V
MAIN
FB
1
2
1
×
-
=
R
V
I
C
I
t
V
ESR MAX
(
DIP MAX
(
×
PULSE
×
OUT MIN
(
PULSE
PULSE
DIP MAX
(
)
)
)
)
×
2
2
V
V
V
V
×
I
R
V
I
t
C
DIP
DIP ESR
=
DI( )
×
DIP ESR
(
PULSE
ESR
DIP( )
PULSE
PULSE
OUT
+
(
)
)
=
R
V
I
C
I
V
V
V
V
f
ESR MAX
(
RIPPLE MAX
×
2
PEAK
OUT MIN
(
MAIN
RIPPLE MAX
MAIN
IN
MAIN
OSC
)
(
)
)
(
)
×
×
×
2
-
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