![](http://datasheet.mmic.net.cn/370000/MAX1533A_datasheet_16707855/MAX1533A_14.png)
M
High-Efficiency, 5x Output, Main Power-Supply
Controllers for Notebook Computers
14
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Pin Description (continued)
PIN
MAX1533A
MAX1537A
NAME
FUNCTION
10
12
PGOOD
Open-Drain Power-Good Output. PGOOD is low if either output is more than 10%
(typ) below the normal regulation point, during soft-start, and in shutdown. PGOOD is
delayed on the rising edge by the PGDLY one-shot timer. PGOOD becomes high
impedance when both SMPS outputs are in regulation.
11
13
UVP
Undervoltage Fault-Protection Control. Connect
UVP
to GND to select the default
overvoltage threshold of 70% of nominal. Connect to V
CC
to disable undervoltage
protection and clear the undervoltage fault latch.
12
14
DH3
High-Side Gate-Driver Output for 3.3V SMPS. DH3 swings from LX3 to BST3.
13
15
BST3
Boost Flying-Capacitor Connection for 3.3V SMPS. Connect to an external capacitor
and diode as shown in Figure 6. An optional resistor in series with BST3 allows the
DH3 pullup current to be adjusted.
14
16
LX3
Inductor Connection for 3.3V SMPS. Connect LX3 to the switched side of the
inductor. LX3 serves as the lower supply rail for the DH3 high-side gate driver.
15
17
OVP
Overvoltage Fault-Protection Control. Connect
OVP
to GND to select the default
overvoltage threshold of +11% above nominal. Connect to V
CC
to disable
overvoltage protection and clear the overvoltage fault latch.
16
18
CSH3
Positive Current-Sense Input for 3.3V SMPS. Connect to the positive terminal of the
current-sense element. Figure 9 describes two different current-sensing options.
17
19
CSL3
Negative Current-Sense Input for 3.3V SMPS. Connect to the negative terminal of the
current-sense element. Figure 9 describes two different current-sensing options.
CSL3 also serves as the bootstrap input for LDO3.
18
20
FB3
Feedback Input for 3.3V SMPS. Connect to GND for fixed 3.3V output. In adjustable
mode, FB3 regulates to 1V.
19
21
LDO3
3.3V Internal Linear-Regulator Output. Bypass with 2.2μF (min) (1μF/20mA). Provides
100mA (min). Power is taken from LDO5. If CSL3 is greater than 3V, the linear
regulator shuts down and LDO3 connects to CSL3 through a 1
Ω
switch rated for
loads up to 200mA.
20
21
22
22
23
24
DL3
PGND
DL5
Low-Side Gate-Driver Output for 3.3V SMPS. DL3 swings from PGND to LDO5.
Power Ground
Low-Side Gate-Driver Output for 5V SMPS. DL5 swings from PGND to LDO5.
23
25
LDO5
5V Internal Linear-Regulator Output. Bypass with 2.2μF (min) (1μF/20mA). Provides
power for the DL_ low-side gate drivers, the DH_ high-side drivers through the BST
diodes, the PWM controller, logic, and reference through the V
CC
pin, as well as the
LDO3 internal 3.3V linear regulator. Provides 100mA (min) for external loads (+25mA
for gate drivers). If CSL5 is greater than 4.5V, the linear regulator shuts down and
LDO5 connects to CSL5 through a 0.75
Ω
switch rated for loads up to 200mA.
24
26
FB5
Feedback Input for 5V SMPS. Connect to GND for fixed 5V output. In adjustable
mode, FB5 regulates to 1V.