參數(shù)資料
型號: MAX1559
廠商: Maxim Integrated Products, Inc.
英文描述: 5-Output Power-Management IC For Low-Cost PDAs
中文描述: 5路輸出電源管理IC,用于低成本PDA
文件頁數(shù): 12/14頁
文件大?。?/td> 526K
代理商: MAX1559
M
where V
DD
is the I/O voltage of the PWM output. The
Thevenin impedance is the sum of resistors R
W
and R
D
:
R
THEV
= R
D
+ R
W
The output voltage (V
OUT
) as a function of the PWM
average voltage (V
THEV
) is:
When using the PWM adjustment method, R
D
isolates
the capacitor from the feedback loop of the MAX1559.
The cutoff frequency of the lowpass filter is defined as:
The cutoff frequency should be at least 2 decades
below the PWM frequency to minimize the induced AC
ripple at the output.
An important consideration is the turn-on transient cre-
ated by the initial charge on the filter capacitor C10.
This capacitor forms a time constant with R
THEV
, which
causes the output to initialize at a higher than intended
voltage. This overshoot can be minimized by scaling
R
D
as high as possible compared to R1 and R2.
Alternately, the μP can briefly keep the LCD disabled
until the PWM voltage has had time to stabilize.
PC Board Layout and Grounding
Careful PC board layout is important for minimizing
ground bounce and noise. Keep the MAX1559
s
ground pin and the ground leads of the input and out-
put capacitors less than 0.2in (5mm) apart. In addition,
keep all connections to FB and LX as short as possible.
In particular, external feedback resistors should be as
close to FB as possible. To minimize output voltage rip-
ple and to maximize output power and efficiency, use a
ground plane and solder GND directly to the ground
plane. Refer to the MAX1559 evaluation kit for a layout
example.
Thermal Considerations
In most applications, the circuit is located on a multilay-
er board and full use of the four or more layers is rec-
ommended. For heat dissipation, connect the exposed
backside pad of the QFN package to a large analog
ground plane, preferably on a surface of the board that
receives good airflow. Typical applications use multiple
ground planes to minimize thermal resistance. Avoid
large AC currents through the analog ground plane.
f
R
C
THEV
=
×
×
1
2
π
V
V
R
R
V
V
R
R
OUT
REF
REF
THEV
THEV
=
×
+
+
×
1
1
2
1
(
)
5-Output Power-Management IC For
Low-Cost PDAs
12
______________________________________________________________________________________
3.3V
MAIN
V
IN
1V
COR1
RS
OUTPUT
RS EXTERNAL RC SET FOR
10ms DELAY FROM 1V GOOD
COR1 NOT ACTIVATED
UNTIL 3.3V IN REGULATION
COR1 DEACTIVATED AND
RS LOW WHEN MAIN
3.3V ACTIVATED
WHEN V
IN
RISES
TO 3.6V
3.3V DEACTIVATED
WHEN V
IN
FALLS
TO 3.0V
FALLS TO 3V
Figure 3.
RS
and Power-On, Power-Off Timing for 3.3V and 1V
Core
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PDF描述
MAX1559ETE 5-Output Power-Management IC For Low-Cost PDAs
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