參數(shù)資料
型號(hào): MAX187ACWE+T
廠商: Maxim Integrated Products
文件頁數(shù): 17/18頁
文件大小: 0K
描述: IC ADC 12BIT SERIAL LP 16SOIC
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 1,000
位數(shù): 12
采樣率(每秒): 75k
數(shù)據(jù)接口: MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 478mW
電壓電源: 單電源
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 16-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 16-SOIC W
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 1 個(gè)單端,單極
MAX187/MAX189
+5V, Low-Power, 12-Bit Serial ADCs
8
Maxim Integrated
Figure 3a. MAX187 Operational Diagram
Figure 4. Equivalent Input Circuit
Figure 3b. MAX189 Operational Diagram
Track/Hold
In track mode, the analog signal is acquired and stored
in the internal hold capacitor. In hold mode, the T/H
switch opens and maintains a constant input to the
ADC’s SAR section.
During acquisition, the analog input AIN charges capaci-
tor CHOLD. Bringing CS low ends the acquisition interval.
At this instant, the T/H switches the input side of CHOLD
to GND. The retained charge on CHOLD represents a
sample of the input, unbalancing the node ZERO at the
comparator’s input.
In hold mode, the capacitive DAC adjusts during the
remainder of the conversion cycle to restore node ZERO
to 0V within the limits of a 12-bit resolution. This action
is equivalent to transferring a charge from CHOLD to the
binary-weighted capacitive DAC, which in turn forms a
digital representation of the analog input signal. At the
conversion’s end, the input side of CHOLD switches back
to AIN, and CHOLD charges to the input signal again.
The time required for the T/H to acquire an input sig-
nal is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens and more time must be
allowed between conversions. Acquisition time is calcu-
lated by:
tACQ = 9 (RS + RIN) 16pF
where RIN = 5kI, RS = the source impedance of the
input signal, and tACQ is never less than 1.5Fs. Source
impedances below 5kI do not significantly affect the AC
performance of the ADC.
Input Bandwidth
The ADCs’ input tracking circuitry has a 4.5MHz small-
signal bandwidth, and an 8V/Fs slew rate. It is possible
to digitize high-speed transient events and measure
periodic signals with bandwidths exceeding the ADC’s
sampling rate by using undersampling techniques. To
avoid aliasing of unwanted high-frequency signals into
the frequency band of interest, an anti-alias filter is rec-
ommended. See the MAX274/MAX275 continuous-time
filters data sheet.
ON
OFF
SHUTDOWN
INPUT
ANALOG INPUT
0 TO +5V
+5V
1
2
3
4
VDD
AIN
SHDN
REF
8
7
6
5
SCLK
DOUT
GND
SERIAL
INTERFACE
4.7F
0.1F
CS
MAX187
AIN
TRACK INPUT
HOLD
CPACKAGE
GND
TRACK
HOLD
RIN
5kI
CHOLD
16pF
-+
CSWITCH
COMPARATOR
ZERO
REF
12-BIT CAPACITIVE DAC
AT THE SAMPLING INSTANT,
THE INPUT SWITCHES FROM
AIN TO GND.
ON
OFF
SHUTDOWN
INPUT
ANALOG INPUT
0 TO +5V
REFERENCE
INPUT
+5V
1
2
3
4
VDD
AIN
SHDN
REF
8
7
6
5
SCLK
DOUT
GND
SERIAL
INTERFACE
0.1F
4.7F
0.1F
CS
MAX189
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