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Detailed Description
The MAX1888 is a three-input decoder with three open-
drain outputs. It is used with the MAX1718 DC-to-DC
controller to offset the CPU core voltage in notebook
computers. The MAX1718 has two dedicated inputs
(POS and NEG) that simplify the task of offsetting its
output voltage. Specifically, the output voltage shifts by
an amount equal to the difference between POS and
NEG multiplied by a scale factor that depends on the
DAC code (refer to the MAX1718 data sheet). The volt-
age between the POS and NEG inputs can be set with
a programmable voltage-divider using the MAX1888 to
connect the bottom resistor of the divider to ground
(see Figure 1.)
Logic Characteristics
The Intel mobile processor specifications require inde-
pendent offset to the CPU core voltage for battery
sleep mode (BSM), performance sleep mode (PSM)
and battery-operating mode (BOM). No offsets are
required for the deeper-sleep mode (
DPSLP
) and per-
formance mode (PERF). Table 1 explicitly describes
the logical operation of the decoder.
The decoder
’
s inputs may come from system-level
logic or directly from the CPU. To interface with low-
voltage logic, the MAX1888
’
s input logic thresholds are
designed with an input-logic high voltage of 1.2V (min)
and an input-logic low voltage of 0.3V (max). The logic
inputs also include 40mV (typ) hysteresis to improve
noise immunity.
The output on-resistance is guaranteed to be less than
100
over the entire supply voltage and temperature
range. When loaded with a total pullup resistance
greater than 10k
, the open-drain output resistance
causes less than 1% error in impedance. If the offset
voltage is set to 5% of the regulated output voltage,
then the effect of the impedance error on the output
voltage is approximately 0.05%, which is negligible in
most applications.
The MAX1888 has rising- and falling-edge propagation
delays of 70ns (typ) and 700ns (typ), respectively.
Since transition times for CPU core voltage are typically
much longer than these intervals, such delays are neg-
ligible. Note the time constant of the rising edge in the
output voltage is set by the capacitance of the open-
drain output transistor and the load impedance (see
the
Typical Operating Characteristics
).
M
Low-Cost Integrated Offset Logic for Notebook
CPU Power Supplies
4
_______________________________________________________________________________________
Figure 1. Simplified Application Circuit; Also Used for
Obtaining Characterization Data; Offset Voltage is a
Percentage of the Output Voltage.
OPEN-DRAIN
DECODER
OUTPUTS
TO
MAX1718
POS
NEG
5V INPUT
V
OUT
PERF
SUS
V
CC
GND
MAX1888
BSM
PSM
BOM
LOW-
VOLTAGE
LOGIC
INPUTS
DPSLP
INPUTS
OUTPUTS
MODE
DPSLP
X
L
L
H
H
PERF
X
L
H
L
H
SUS
H
L
L
L
L
BSM
Hi-Z
L
Hi-Z
Hi-Z
Hi-Z
PSM
Hi-Z
Hi-Z
L
Hi-Z
Hi-Z
BOM
Hi-Z
Hi-Z
Hi-Z
L
Hi-Z
Deeper Sleep
Battery Sleep
Performance Sleep
Battery Operating
Performance
TTable 1. Truth Table