MAX187/MAX189
+5V, Low-Power, 12-Bit Serial ADCs
4
Maxim Integrated
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +5V ±5%; VGND = 0V; unipolar input mode; 75ksps, fCLK = 4.0MHz, external clock (50% duty cycle); MAX187—internal refer-
ence: VREF = 4.096V, 4.7F capacitor at REF pin, or MAX189—external reference: VREF = 4.096V applied to REF pin, 4.7F capacitor
at REF pin; TA = TMIN to TMAX; unless otherwise noted.)
TIMINg CHARACTERISTICS
(VDD = +5V ±5%, TA = TMIN to TMAX; unless otherwise noted.)
Note 1: Tested at VDD = +5V.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 3: MAX187—internal reference, offset nulled; MAX189–external +4.096V reference, offset nulled. Excludes reference errors.
Note 4: Guaranteed by design. Not subject to production testing.
Note 5: External load should not change during conversion for specified ADC accuracy.
Note 6: DC test, measured at 4.75V and 5.25V only.
Note 7: To guarantee acquisition time, tACQ is the maximum time the device takes to acquire the signal, and is also the minimum-
time needed for the signal to be acquired.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
uNITS
DIgITAL OuTPuT (DOuT)
Output Voltage Low
VOL
ISINK = 5mA
0.4
V
ISINK = 16mA
0.3
Output Voltage High
VOH
ISOURCE = 1mA
4
V
Three-State Leakage Current
IL
VCS = 5V
Q
10
F
A
Three-State Output Capacitance
COUT
VCS = 5V (Note 4)
15
pF
POWER REQuIREMENTS
Supply Voltage
VDD
4.75
5.25
V
Supply Current
IDD
Operating mode
MAX187
1.5
2.5
mA
MAX189
1.0
2.0
Power-down mode
2
10
F
A
Power-Supply Rejection
PSR
VDD = +5V Q5%; external reference,
4.096V; full-scale input (Note 6)
Q
0.06
Q
0.5
mV
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
uNITS
Track/Hold Acquisition Time
tACQ
CS = high (Note7)
1.5
s
SCLK Fall to Output Data Valid
tDQ
CLOAD = 100pF
MAX18_ _C/E
20
150
ns
MAX18_ _M
20
200
CS Fall to Output Enable
tDV
CLOAD = 100pF
100
ns
CS Rise to Output Disable
tTR
CLOAD = 100pF
100
ns
SCLK Clock Frequency
tSCLK
5
MHz
SCLK Pulse Width High
tCH
100
ns
SCLK Pulse Width Low
tCL
100
ns
SCLK Low to CS Fall Setup Time
tCSO
50
ns
CS Pulse Width
tCS
500
ns