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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | MAX191BCWG+ |
| 寤犲晢锛� | Maxim Integrated Products |
| 鏂囦欢闋佹暩(sh霉)锛� | 8/24闋� |
| 鏂囦欢澶у皬锛� | 0K |
| 鎻忚堪锛� | IC ADC 12BIT 100KSPS W/REF24SOIC |
| 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 30 |
| 浣嶆暩(sh霉)锛� | 12 |
| 閲囨ǎ鐜囷紙姣忕锛夛細 | 100k |
| 鏁�(sh霉)鎿�(j霉)鎺ュ彛锛� | MICROWIRE?锛屽苟鑱�(li谩n)锛孮SPI?锛屼覆琛�锛孲PI? |
| 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩細 | 1 |
| 鍔熺巼鑰楁暎锛堟渶澶э級锛� | 941mW |
| 闆诲闆绘簮锛� | 闆� ± |
| 宸ヤ綔婧害锛� | 0°C ~ 70°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 24-SOIC锛�0.295"锛�7.50mm 瀵級 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 24-SOIC W |
| 鍖呰锛� | 绠′欢 |
| 杓稿叆鏁�(sh霉)鐩拰椤炲瀷锛� | 2 鍊�(g猫)鍠锛屽柈妤�锛�2 鍊�(g猫)鍠锛岄洐妤�锛�1 鍊�(g猫)宸垎锛屽柈妤碉紱1 鍊�(g猫)宸垎锛岄洐妤� |
| 鐢�(ch菐n)鍝佺洰閷勯爜闈細 | 1393 (CN2011-ZH PDF) |
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MAX191
fSCLK(MAX) = (1/2) x 1/ (tsu(M) + t22)
where tsu(M) is the minimum data-setup time re-
quired at the serial data input to the P. For example,
Motorola鈥檚 MC68HC11A8 data book specifies a 100ns
minimum data-setup time. Using the worst case for a
military grade part of t22 = 280ns (see Timing
Characteristics) and substituting in the above equation
indicates a maximum SCLK frequency of 1.3MHz.
Using the MAX191 with SPI, QSPI and
MICROWIRE Serial Interfaces
Figure 13 shows interface connections to the MAX191
for common serial-interface standards.
SPI and MICROWIRE (CPOL=0, CPHA=0)
The MAX191 is compatible with SPI, QSPI and
MICROWIRE serial-interface standards. When using SPI
or QSPI, two modes are available to interface with the
MAX191. You can set CPOL = 0 and CPHA = 0 (Figure
14a), or set CPOL = 1 and CPHA = 1 (Figure 14b). When
using CPOL = 0 and CPHA = 0, the conversion begins
on the first falling edge of SCLK following CS going low.
Data is available from DOUT on the rising edge of SCLK,
and transitions on the falling edge. Two consecutive
1-byte reads are required to get the full 12 bits from the
ADC. The first byte contains the following, in this order: a
leading unknown bit (DOUT will still be high-impedance
on the first bit), a 0, and the six MSBs. The second byte
contains the remaining six LSBs and two trailing 0s.
SPI (CPOL=1, CPHA=1)
Setting CPOL = 1 and CPHA = 1 starts the clock high
during a read instruction. The MAX191 will shift out a
leading 0 followed by the 12 data bits and three trailing
0s (Figure 14b).
QSPI
Unlike SPI, which requires two 1-byte reads to acquire
the 12 bits of data from the ADC, QSPI allows the mini-
mum number of clock cycles required to clock in the
data (Figure 15).
TMS320 Serial Interface
Figure 13d shows the pin connections to interface the
MAX191 to the TMS320. Since the MAX191 makes data
available on the rising edge of SCLK and the TMS320
shifts data in on the falling edge of CLKR, use CLKX of the
DSP to drive SCLK, and CLKX to drive the DSP鈥檚 CLKR
input. The inverter鈥檚 propagation delay also provides more
data-setup time at the DSP. For example, with no inverter
delay, and using t22 = 280ns and fSCLK = 1.6MHz, the
available setup time before the SCLK transition is:
setup time = 1/ (2 x fSCLK) - t22 = 1/ (2 x 1.6E6) - 280ns = 32ns
This still exceeds the 13ns minimum DR setup time before
the CLKR goes low (tsu(DR)), however, a generic 74HC04
provides an additional 20ns setup time (see Figure 13d).
Figure 16 shows the DSP interface timing characteris-
tics. The DSP begins clocking data in on the falling
edge of CLKR after the falling edge of SSTRB.
Low-Power, 12-Bit Sampling ADC
with Internal Reference and Power-Down
16
______________________________________________________________________________________
DOUT
LEADING
ZERO
MSB
D9
D10
D7
D8
D5
D6
D3
D4
D1
D2
LSB
CS
SCLK
HIGH-Z
1ST BYTE READ
2ND BYTE READ
HIGH-Z
a. CPOL = 0, CPHA = 0
DOUT
LEADING
ZERO
MSB
D9
D10
D7
D8
D5
D6
D3
D4
D1
D2
LSB
CS
SCLK
HIGH-Z
b. CPOL = 1, CPHA = 1
Figure 14. SPI/MICROWIRE Serial-Interface Timing
鐩搁棞(gu膩n)PDF璩囨枡 |
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鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| MAX191BCWG+ | 鍔熻兘鎻忚堪:妯℃暩(sh霉)杞�(zhu菐n)鎻涘櫒 - ADC 12Bit 100ksps 5V Precision ADC RoHS:鍚� 鍒堕€犲晢:Texas Instruments 閫氶亾鏁�(sh霉)閲�:2 绲�(ji茅)妲�(g貌u):Sigma-Delta 杞�(zhu菐n)鎻涢€熺巼:125 SPs to 8 KSPs 鍒嗚鲸鐜�:24 bit 杓稿叆椤炲瀷:Differential 淇″櫔姣�:107 dB 鎺ュ彛椤炲瀷:SPI 宸ヤ綔闆绘簮闆诲:1.7 V to 3.6 V, 2.7 V to 5.25 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:VQFN-32 |
| MAX191BCWG+T | 鍔熻兘鎻忚堪:妯℃暩(sh霉)杞�(zhu菐n)鎻涘櫒 - ADC 12Bit 100ksps 5V Precision ADC RoHS:鍚� 鍒堕€犲晢:Texas Instruments 閫氶亾鏁�(sh霉)閲�:2 绲�(ji茅)妲�(g貌u):Sigma-Delta 杞�(zhu菐n)鎻涢€熺巼:125 SPs to 8 KSPs 鍒嗚鲸鐜�:24 bit 杓稿叆椤炲瀷:Differential 淇″櫔姣�:107 dB 鎺ュ彛椤炲瀷:SPI 宸ヤ綔闆绘簮闆诲:1.7 V to 3.6 V, 2.7 V to 5.25 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:VQFN-32 |
| MAX191BCWG-T | 鍔熻兘鎻忚堪:妯℃暩(sh霉)杞�(zhu菐n)鎻涘櫒 - ADC Integrated Circuits (ICs) RoHS:鍚� 鍒堕€犲晢:Texas Instruments 閫氶亾鏁�(sh霉)閲�:2 绲�(ji茅)妲�(g貌u):Sigma-Delta 杞�(zhu菐n)鎻涢€熺巼:125 SPs to 8 KSPs 鍒嗚鲸鐜�:24 bit 杓稿叆椤炲瀷:Differential 淇″櫔姣�:107 dB 鎺ュ彛椤炲瀷:SPI 宸ヤ綔闆绘簮闆诲:1.7 V to 3.6 V, 2.7 V to 5.25 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:VQFN-32 |
| MAX191BENG | 鍔熻兘鎻忚堪:妯℃暩(sh霉)杞�(zhu菐n)鎻涘櫒 - ADC RoHS:鍚� 鍒堕€犲晢:Texas Instruments 閫氶亾鏁�(sh霉)閲�:2 绲�(ji茅)妲�(g貌u):Sigma-Delta 杞�(zhu菐n)鎻涢€熺巼:125 SPs to 8 KSPs 鍒嗚鲸鐜�:24 bit 杓稿叆椤炲瀷:Differential 淇″櫔姣�:107 dB 鎺ュ彛椤炲瀷:SPI 宸ヤ綔闆绘簮闆诲:1.7 V to 3.6 V, 2.7 V to 5.25 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:VQFN-32 |
| MAX191BENG+ | 鍔熻兘鎻忚堪:妯℃暩(sh霉)杞�(zhu菐n)鎻涘櫒 - ADC 12Bit 100ksps 5V Precision ADC RoHS:鍚� 鍒堕€犲晢:Texas Instruments 閫氶亾鏁�(sh霉)閲�:2 绲�(ji茅)妲�(g貌u):Sigma-Delta 杞�(zhu菐n)鎻涢€熺巼:125 SPs to 8 KSPs 鍒嗚鲸鐜�:24 bit 杓稿叆椤炲瀷:Differential 淇″櫔姣�:107 dB 鎺ュ彛椤炲瀷:SPI 宸ヤ綔闆绘簮闆诲:1.7 V to 3.6 V, 2.7 V to 5.25 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:VQFN-32 |
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