參數(shù)資料
型號(hào): MAX192AEWP+
廠商: Maxim Integrated Products
文件頁數(shù): 4/24頁
文件大?。?/td> 0K
描述: IC ADC 10BIT SERIAL 20-SOIC
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 36
類型: 數(shù)據(jù)采集系統(tǒng)(DAS),ADC
分辨率(位): 10 b
采樣率(每秒): 133k
數(shù)據(jù)接口: MICROWIRE?,QSPI?,串行,SPI?
電壓電源: 單電源
電源電壓: ±5V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 20-SOIC W
包裝: 管件
MAX192
Low-Power, 8-Channel,
Serial 10-Bit ADC
12
______________________________________________________________________________________
SSTRB
CS
SCLK
DIN
DOUT
1
4
8
12
16
20
24
START SEL2 SEL1 SEL0
UNI/
BIP
SGL/
DIF
PD1
PD0
B9
MSB
B8
B7
B6
B5
B4
B3
B2
B1
B0
LSB
S1
SO
ACQUISITION
1.5s (CLK = 2MHz)
IDLE
FILLED WITH
ZEROS
IDLE
CONVERSION
tACQ
A/D STATE
RB1
RB2
RB3
RB2
RB3
CS
SCLK
DIN
DOUT
tCSH
tCSS
tCL
tDS
tDH
tDV
tCH
tDO
tTR
tCSH
Figure 6. 24-Bit External Clock Mode Conversion Timing (SPI, QSPI and Microwire Compatible)
Figure 7. Detailed Serial-Interface Timing
Pulling CS high prevents data from being clocked into
the MAX192 and three-states DOUT, but it does not
adversely affect an internal clock-mode conversion
already in progress. When internal clock mode is
selected, SSTRB does not go into a high-impedance
state when CS goes high.
Figure 10 shows the SSTRB timing in internal clock
mode. In internal clock mode, data can be shifted in
and out of the MAX192 at clock rates exceeding
4.0MHz, provided that the minimum acquisition time,
tAZ, is kept above 1.5s.
Data Framing
The falling edge of CS does not start a conversion on
the MAX192. The first logic high clocked into DIN is inter-
preted as a start bit and defines the first bit of the control
byte. A conversion starts on the falling edge of SCLK,
after the eighth bit of the control byte (the PD0 bit) is
clocked into DIN. The start bit is defined as:
The first high bit clocked into DIN with CS low any-
time the converter is idle, e.g. after VDD is applied.
OR
The first high bit clocked into DIN after bit 3 of a
conversion in progress is clocked onto the DOUT pin.
If a falling edge on CS forces a start bit before bit 3
(B3) becomes available, then the current conversion
will be terminated and a new one started. Thus, the
fastest the MAX192 can run is 15 clocks per conver-
sion. Figure 11a shows the serial-interface timing nec-
essary to perform a conversion every 15 SCLK cycles
in external clock mode. If CS is low and SCLK is contin-
uous, guarantee a start bit by first clocking in 16 zeros.
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