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  • 參數(shù)資料
    型號: MAX192BEPP
    廠商: MAXIM INTEGRATED PRODUCTS INC
    元件分類: ADC
    英文描述: Fixed-Point Digital Signal Processor 532-FCBGA
    中文描述: 8-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDIP20
    封裝: PLASTIC, DIP-20
    文件頁數(shù): 15/24頁
    文件大?。?/td> 201K
    代理商: MAX192BEPP
    Power-Down
    Choosing Power-Down Mode
    You can save power by placing the converter in a
    low-current shutdown state between conversions.
    Select full power-down or fast power-down mode via
    bits 1 and 0 of the DIN control byte with
    SHDN
    either
    high or floating (see Tables 3 and 6). Pull
    SHDN
    low at
    any time to shut down the converter completely.
    SHDN
    overrides bits 1 and 0 of DIN word (see Table 7).
    Full power-down mode turns off all chip functions that
    draw quiescent current, typically reducing I
    DD
    to 2μA.
    Fast power-down mode turns off all circuitry except the
    bandgap reference. With the fast power-down mode, the
    supply current is 30μA. Power-up time can be shortened
    to 5μs in internal compensation mode.
    In both software shutdown modes, the serial interface
    remains operational, however, the ADC will not convert.
    Table 5 illustrates how the choice of reference-buffer
    compensation and power-down mode affects both
    power-up delay and maximum sample rate.
    In external compensation mode, the power-up time is
    20ms with a 4.7μF compensation capacitor when the
    capacitor is fully discharged. In fast power-down, you
    can eliminate start-up time by using low-leakage capaci-
    M
    Low-Power, 8-Channel,
    S erial 10-Bit ADC
    ______________________________________________________________________________________
    15
    POWERED UP
    FULL
    POWER-
    DOWN
    POWERED
    UP
    POWERED UP
    DATA VALID
    (10 + 2 DATA BITS)
    DATA VALID
    (10 + 2 DATA BITS)
    DATA INVALID
    VALID
    EXTERNAL
    EXTERNAL
    INTERNAL
    S X X X X X 1 1
    S
    0 1
    X
    X
    X
    X
    X
    X X X X X
    S
    1 1
    FAST
    POWER-DOWN
    MODE
    DOUT
    DIN
    CLOCK
    MODE
    SHDN
    SETS EXTERNAL
    CLOCK MODE
    SETS EXTERNAL
    CLOCK MODE
    SETS FAST
    POWER-DOWN
    MODE
    Figure 12a. Timing Diagram Power-Down Modes, External Clock
    FULL
    POWER-DOWN
    POWERED
    UP
    POWERED UP
    DATA VALID
    DATA VALID
    INTERNAL CLOCK MODE
    S X X X X X 1 0
    S
    0 0
    X
    X
    X
    X
    X
    S
    MODE
    DOUT
    DIN
    CLOCK
    MODE
    SETS INTERNAL
    CLOCK MODE
    SETS FULL
    POWER-DOWN
    CONVERSION
    CONVERSION
    SSTRB
    Figure 12b. Timing Diagram Power-Down Modes, Internal Clock
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