參數(shù)資料
型號(hào)： MAX19505EVKIT+
廠商： Maxim Integrated Products
文件頁數(shù)： 32/35頁
文件大?。?/td> 0K
描述： KIT EVALUATION FOR MAX1950 ADC
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 1
ADC 的數(shù)量： 2
位數(shù)： 8
采樣率（每秒）： 65M
數(shù)據(jù)接口： 串行，并聯(lián)
輸入范圍： 0.4 ~ 1.4 V
在以下條件下的電源（標(biāo)準(zhǔn)）： 43mW @ 65MSPS，1.8V
工作溫度： -40°C ~ 85°C
已用 IC / 零件： MAX19505
已供物品： 板，軟件
MAX19505
Dual-Channel, 8-Bit, 65Msps ADC
6
_______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VOVDD = 1.8V, internal reference, differential clock, VCLK = 1.5VP-P, fCLK = 65MHz, AIN = -0.5dBFS, data output termination
= 50
, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER-MANAGEMENT CHARACTERISTICS
Wake-Up Time from Shutdown
tWAKE
Internal reference, CREFIO = 0.1F (10
τ)5
ms
Wake-Up Time from Standby
tWAKE
Internal reference
15
s
SERIAL-PORT INTERFACE TIMING (Note 2) (Figure 7)
SCLK Period
tSCLK
50
ns
SCLK to
CS Setup Time
tCSS
10
ns
SCLK to
CS Hold Time
tCSH
10
ns
SDIN to SCLK Setup Time
tSDS
Serial-data write
10
ns
SDIN to SCLK Hold Time
tSDH
Serial-data write
0
ns
SCLK to SDIN Output Data Delay
tSDD
Serial-data read
10
ns
TIMING CHARACTERISTICS—DUAL BUS PARALLEL MODE (Figure 9) (Default Timing, see Table 5)
Clock Pulse-Width High
tCH
7.69
ns
Clock Pulse-Width Low
tCL
7.69
ns
Clock Duty Cycle
tCH/tCLK
30 to 70
%
CL = 10pF, VOVDD = 1.8V (Note 2)
3.4
5.3
7.1
Data Delay After Rising Edge of
CLK+
tDD
CL = 10pF, VOVDD = 3.3V
4.1
ns
Data to DCLK Setup Time
tSETUP
CL = 10pF, VOVDD = 1.8V (Note 2)
12.8
13.4
ns
Data to DCLK Hold Time
tHOLD
CL = 10pF, VOVDD = 1.8V (Note 2)
1.4
2.0
ns
TIMING CHARACTERISTICS—MULTIPLEXED BUS PARALLEL MODE (Figure 10) (Default Timing, see Table 5)
Clock Pulse-Width High
tCH
7.69
ns
Clock Pulse-Width Low
tCL
7.69
ns
Clock Duty Cycle
tCH/tCLK
30 to 70
%
CL = 10pF, VOVDD = 1.8V (Note 2)
3.3
5.2
7.0
Data Delay After Rising Edge of
CLK+
tDD
CL = 10pF, VOVDD = 3.3V
4.0
ns
Data to DCLK Setup Time
tSETUP
CL = 10pF, VOVDD = 1.8V (Note 2)
5.0
5.9
ns
Data to DCLK Hold Time
tHOLD
CL = 10pF, VOVDD = 1.8V (Note 2)
1.2
1.8
ns
DCLK Duty Cycle
tDCH/tCLK
CL = 10pF, VOVDD = 1.8V (Note 2)
44
50
56
%
MUX Data Duty Cycle
tCHA/tCLK
CL = 10pF, VOVDD = 1.8V (Note 2)
44
50
56
%
TIMING CHARACTERISTICS—SYNCHRONIZATION (Figure 12)
Setup Time for Valid Clock Edge
tSUV
Edge mode (Note 2)
0.7
ns
Hold-Off Time for Invalid Clock
Edge
tSDH
Edge mode (Note 2)
0.5
ns
Minimum Synchronization Pulse
Width
Relative to input clock period
2
Cycles
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參數(shù)描述
MAX19505EVKIT+ 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 MAX19505-07/15-17 Eval Kit RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評(píng)估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V
MAX19506ETM+ 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 8-Bit 2Ch 100Msps 1.8V Precision ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
MAX19506ETM+T 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 8-Bit 2Ch 100Msps 1.8V Precision ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
MAX19506EVKIT+ 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 MAX19505-07/15-17 Eval Kit RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評(píng)估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V
MAX19507ETM+ 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 8-Bit 2Ch 130Msps 1.8V Precision ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
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