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    參數(shù)資料
    型號(hào): MAX195BEWE
    廠商: MAXIM INTEGRATED PRODUCTS INC
    元件分類: ADC
    英文描述: 16-Bit, 85ksps ADC with 10レA Shutdown
    中文描述: 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO16
    封裝: 0.300 INCH, PLASTIC, SOIC-16
    文件頁數(shù): 13/28頁
    文件大小: 311K
    代理商: MAX195BEWE
    M
    16-Bit, 85ksps ADC with 10μA S hutdown
    ______________________________________________________________________________________
    13
    INPUT
    SIGNAL
    1N914
    DIODE
    CLAMPS
    +5V
    AIN
    MAX195
    -5V
    VSSA
    VDDA
    +15V
    -15V
    10
    Figure 12. Analog Input Protection for Overvoltage or Improper Supply Sequence
    REF and AIN Input Protec tion
    The REF and AIN signals should not exceed the
    MAX195 supply rails. If this can occur, diode clamp the
    signal to the supply rails. Use silicon diodes and a 10
    current-limiting resistor (Figures 10 and 12) or Schottky
    diodes without the resistor.
    When using the current-limiting resistor, place the resis-
    tor between the appropriate input (AIN or REF) and any
    bypass capacitor. While this results in AC transients at
    the input due to dynamic input currents, the transients
    settle quickly and do not affect conversion results.
    Improperly placing the bypass capacitor directly at the
    input forms an RC lowpass filter with the current-limiting
    resistor, which averages the dynamic input current and
    causes linearity errors.
    Analog Input
    The MAX195 uses a capacitive DAC that provides an
    inherent track/hold function. The input impedance is
    typically 30
    in series with 250pF in unipolar mode and
    50
    in series with 125pF in bipolar mode.
    Input Range
    The analog input range can be either unipolar (0V to
    V
    REF
    ) or bipolar (-V
    REF
    to V
    REF
    ), depending on the
    state of the BP/UP/
    SHDN
    pin (see Digital Interface sec-
    tion). The reference range is 0V to VDDA. When choos-
    ing the reference voltage, the equivalent MAX195 input
    noise (40μV
    RMS
    in unipolar mode, 80μV
    RMS
    in bipolar
    mode) should be considered.
    Input Acquisition and Settling
    Four conversion-clock periods are allocated for acquir-
    ing the input signal. At the highest conversion rate, four
    clock periods is 2.4μs. If more than three clock cycles
    have occurred since the end of the previous conver-
    sion, conversion begins on the next falling clock edge
    after
    CONV
    goes low. Otherwise, bringing
    CONV
    low
    begins a conversion on the fourth falling clock edge
    after the previous conversion. This scheme ensures the
    minimum input acquisition time is four clock periods.
    Most applications require an input buffer amplifier. If
    the input signal is multiplexed, the input channel should
    be switched near the beginning of a conversion, rather
    than near the end of or after a conversion (Figure 13).
    This allows time for the input buffer amplifier to respond
    to a large step change in input signal. The input amplifi-
    er must have a high enough slew rate to complete the
    required output voltage change before the beginning of
    the acquisition time.
    At the beginning of acquisition, the capacitive DAC is
    connected to the amplifier output, causing some output
    disturbance. Ensure that the sampled voltage has set-
    tled to within the required limits before the end of the
    acquisition time. If the frequency of interest is low, AIN
    can be bypassed with a large enough capacitor to
    charge the capacitive DAC with very little change in
    voltage (Figure 14). However, for AC use, AIN must be
    driven by a wideband buffer (at least 10MHz), which
    must be stable with the DAC’s capacitive load (in paral-
    lel with any AIN bypass capacitor used) and also must
    settle quickly (Figure 15 or 16).
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