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參數(shù)資料
| 型號： | MAX196BEWI+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 12/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAS 12BIT 6CH 28-SOIC |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 1,000 |
| 類型： | 數(shù)據(jù)采集系統(tǒng)（DAS） |
| 分辨率（位）： | 12 b |
| 采樣率（每秒）： | 100k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 電壓電源： | 單電源 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 28-SOIC W |
| 包裝： | 帶卷 (TR) |
MAX196/MAX198
Multirange, Single +5V, 12-Bit DAS
with 12-Bit Bus Interface
_______________________________________________________________________________________
5
Note 1:
DD = 5.0V. Performance at power-supply tolerance limits guaranteed by Power-Supply
Rejection test. Tested for the ±10V (MAX196) and ±4.096V (MAX198) input ranges.
Note 2:
External reference: VREF = 4.096V, offset error nulled, ideal last code transition = FS - 3/2LSB.
Note 3:
Ground “on” channel; sine wave applied to all “off” channels.
Note 4:
Maximum full-power input frequency for 1LSB error with 10ns jitter = 3kHz.
Note 5:
Guaranteed by design. Not tested.
Note 6:
Use static loads only.
Note 7:
Tested using internal reference.
Note 8:
PSRR measured at full-scale.
Note 9:
External acquisition timing: starts at data valid at ACQMOD = low control byte; ends at rising edge of WR with ACQMOD
= high control byte.
Note 10: Not subject to production testing. Provided for design guidance only.
Note 11: All input control signals specified with tR = tF = 5ns from a voltage level of 0.8V to 2.4V.
Note 12: tDO is measured with the load circuits of Figure 2 and defined as the time required for an output to cross 0.8V or 2.4V.
Note 13: tTR is defined as the time required for the data lines to change by 0.5V.
TIMING CHARACTERISTICS
(VDD = 5V ±5%; unipolar/bipolar range; external reference mode, VREF = 4.096V; 4.7F at REF pin; external clock, fCLK = 2.0MHz
with 50% duty cycle; TA = TMIN to TMAX; unless otherwise noted.)
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 5V ±5%; unipolar/bipolar range; external reference mode, VREF = 4.096V; 4.7F at REF pin; external clock, fCLK = 2.0MHz
with 50% duty cycle; TA = TMIN to TMAX; unless otherwise noted. Typical values are at TA = +25°C.)
Three-State Output Capacitance
COUT
15
pF
(Note 5)
Output High Voltage
VOH
VDD - 1
V
VDD = 4.75V, ISOURCE = 1mA
Output Low Voltage
VOL
0.4
V
VDD = 4.75V, ISINK = 1.6mA
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
CONDITIONS
DIGITAL OUTPUTS (D11–D0, INT)
RD Low to Output Data Valid
tDO
120
ns
Figure 2, CL = 100pF (Note 12)
Data Valid to WR Setup
Data Valid to WR Hold
tDH
0
ns
tDS
60
ns
CLK to WR Setup Time
CLK to WR Hold Time
tCWH
50
ns
tCWS
100
ns
CS to RD Setup Time
CS to RD Hold Time
tCSRH
0
ns
tCSRS
0
ns
CS to WR Setup Time
CS to WR Hold Time
tCSWH
0
ns
tCSWS
0
ns
WR Pulse Width
tWR
80
ns
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
CS Pulse Width
tCS
80
ns
RD Low to INT High Delay
tINT1
120
ns
RD High to Output Disable
tTR
CONDITIONS
70
ns
(Note 13)
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