參數(shù)資料
型號: MAX19706ETM+T
廠商: Maxim Integrated Products
文件頁數(shù): 6/37頁
文件大小: 0K
描述: IC ANLG FRNT END 48-TQFN
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 2,500
位數(shù): 10
通道數(shù): 4
功率(瓦特): 49.5mW
電壓 - 電源,模擬: 2.7 V ~ 3.3 V
電壓 - 電源,數(shù)字: 1.8 V ~ 3.3 V
封裝/外殼: 48-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 48-TQFN-EP(7x7)
包裝: 帶卷 (TR)
AUX-DAC DIFFERENTIAL NONLINEARITY
MAX19706
toc40
DIGITAL INPUT CODE
DNL
(LSB)
3072
2048
1024
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
-0.8
0
4096
AUX-ADC INTEGRAL NONLINEARITY
MAX19706
toc41
DIGITAL OUTPUT CODE
INL
(LSB)
896
768
512 640
256 384
128
1.5
1.0
0.5
0
-0.5
-1.0
-1.5
2.0
-2.0
0
1024
AUX-ADC DIFFERENTIAL NONLINEARITY
MAX19706
toc42
DIGITAL OUTPUT CODE
DNL
(LSB)
896
768
512 640
256 384
128
-0.4
0
0.4
0.8
-0.8
01024
MAX19706
10-Bit, 22Msps, Ultra-Low-Power
Analog Front-End
14
______________________________________________________________________________________
PIN
NAME
FUNCTION
1
REFP
Upper Reference Voltage. Bypass with a 0.33F capacitor to GND as close to REFP as possible.
2, 8, 11, 31,
33, 39, 43
VDD
Analog Supply Voltage. Bypass VDD to GND with a combination of a 2.2F capacitor in parallel with
a 0.1F capacitor.
3
IAP
Channel-IA Positive Analog Input. For single-ended operation, connect signal source to IAP.
4
IAN
Channel-IA Negative Analog Input. For single-ended operation, connect IAN to COM.
5, 7, 12, 32, 42
GND
Analog Ground. Connect all GND pins to ground plane.
6
CLK
Conversion Clock Input. Clock signal for both receive ADCs and transmit DACs.
9
QAN
Channel-QA Negative Analog Input. For single-ended operation, connect QAN to COM.
Pin Description
AUX-DAC OUTPUT VOLTAGE
vs. OUTPUT SINK CURRENT
MAX19706
toc37
OUTPUT SINK CURRENT (mA)
OUTPUT
VOLTAGE
(V)
10
1
0.1
0.01
0.5
1.0
1.5
2.0
2.5
3.0
0
0.001
100
AUX-DAC SETTLING TIME
MAX19706
toc38
500ns/div
500mV/div
STEP FROM 1/4FS TO 3/4FS
AUX-DAC INTEGRAL NONLINEARITY
MAX19706
toc39
DIGITAL INPUT CODE
INL
(LSB)
3072
2048
1024
-1.5
-1.0
-0.5
0
0.5
1.0
1.5
2.0
-2.0
04096
Typical Operating Characteristics (continued)
(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL
≈ 10pF on all digital outputs, fCLK = 22MHz (50% duty cycle), Rx ADC input
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN =
CCOM = 0.33F, TA = +25°C, unless otherwise noted.)
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