參數(shù)資料
型號(hào): MAX197BEWI+T
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 14/16頁(yè)
文件大小: 0K
描述: IC DAS 12BIT SNGL 28-SOIC
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 1,000
類型: 數(shù)據(jù)采集系統(tǒng)(DAS)
分辨率(位): 12 b
采樣率(每秒): 100k
數(shù)據(jù)接口: 并聯(lián)
電壓電源: 單電源
電源電壓: 4.75 V ~ 5.25 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 28-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 28-SOIC W
包裝: 帶卷 (TR)
MAX197
Multi-Range (±10V, ±5V, +10V, +5V),
Single +5V, 12-Bit DAS with 8+4 Bus Interface
_______________________________________________________________________________________
7
______________________________________________________________Pin Description
Digital Ground
DGND
28
+5V Supply. Bypass with 0.1F capacitor to AGND.
VDD
27
INT goes low when conversion is complete and output data is ready.
INT
24
Bandgap Voltage-Reference Output/External Adjust Pin. Bypass with a 0.01F capacitor to AGND. Connect
to VDD when using an external reference at the REF pin.
REFADJ
25
Reference Buffer Output/ADC Reference Input. In internal reference mode, the reference buffer provides a
4.096V nominal output, externally adjustable at REFADJ. In external reference mode, disable the internal
buffer by pulling REFADJ to VDD.
REF
26
Three-State Digital I/O. D2 output (HBEN = low), D10 output (HBEN = high).
D2/D10
12
Three-State Digital I/O. D1 output (HBEN = low), D9 output (HBEN = high).
D1/D9
13
Three-State Digital I/O. D0 output (HBEN = low), D8 output (HBEN = high). D0 = LSB.
D0/D8
14
Analog Ground
AGND
15
Analog Input Channels
CH0–CH7
16–23
Used to multiplex the 12-bit conversion result. When high, the 4 MSBs are multiplexed on the data bus;
when low, the 8 LSBs are available on the bus.
HBEN
5
Shutdown. Puts the device into full power-down (FULLPD) mode when pulled low.
SHDN
6
Three-State Digital I/O
D7–D4
7–10
Three-State Digital I/O. D3 output (HBEN = low), D11 output (HBEN = high).
D3/D11
11
If CS is low, a falling edge on RD will enable a read operation on the data bus.
RD
4
When CS is low, in the internal acquisition mode, a rising edge on WR latches in configuration data and starts an
acquisition plus a conversion cycle. When CS is low, in the external acquisition mode, the first rising edge on
WR starts an acquisition and a second rising edge on WR ends acquisition and starts a conversion cycle.
WR
3
PIN
Chip Select, active low.
CS
2
Clock Input. In external clock mode, drive CLK with a TTL/CMOS compatible clock. In internal clock mode,
place a capacitor from this pin to ground to set the internal clock frequency; fCLK = 1.56MHz typical with
CCLK = 100pF.
CLK
1
FUNCTION
NAME
100k
510k
24k
REFADJ
+5V
0.01
F
MAX197
Figure 1. Reference-Adjust Circuit
3k
3k
DOUT
+5V
a. HIGH-Z TO VOH AND VOL TO VOH
b. HIGH-Z TO VOL AND VOH TO VOL
CLOAD
Figure 2. Load Circuits for Enable Time
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