參數(shù)資料
型號(hào): MAX199ACWI+T
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 3/16頁(yè)
文件大小: 0K
描述: IC DAS 12BIT 8CH 28-SOIC
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 1,000
類型: 數(shù)據(jù)采集系統(tǒng)(DAS)
分辨率(位): 12 b
采樣率(每秒): 100k
數(shù)據(jù)接口: 并聯(lián)
電壓電源: 單電源
電源電壓: 4.75 V ~ 5.25 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 28-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 28-SOIC W
包裝: 帶卷 (TR)
How to Read a Conversion
A standard interrupt signal, INT, is provided to allow the
device to flag the P when the conversion has ended
and a valid result is available. INT goes low when the
conversion is complete and the output data is ready
(Figures 5 and 6). It returns high on the first read cycle
or if a new control byte is written.
Clock Modes
The MAX199 operates with either an internal or an
external clock. Control bits (D6, D7) select either inter-
nal or external clock mode. Once the desired clock
mode is selected, changing these bits to program
power-down will not affect the clock mode. In each
mode, internal or external acquisition can be used. At
power-up, the MAX199 defaults to external clock mode.
Internal Clock Mode
Select internal clock mode to free the P from the
burden of running the SAR conversion clock. To select
this mode, write the control byte with D7 = 0 and D6 = 1.
A 100pF capacitor between the CLK pin and ground
sets this frequency to 1.56MHz nominal. Figure 7
shows a linear relationship between the internal clock
period and the value of the external capacitor used.
MAX199
Multi-Range (±4V, ±2V, +4V, +2V),
+5V Supply, 12-Bit DAS with 8+4 Bus Interface
______________________________________________________________________________________
11
tCS
tCSWS
tWR
tACQI
tCONV
tDH
tDS
tINT1
tD0
tD01
tTR
tCSHW
tCSRS
tCSRH
ACQMOD = "1"
CS
WR
D7–D0
INT
RD
HBEN
DOUT
ACQMOD = "0"
HIGH / LOW
BYTE VALID
HIGH-Z
HIGH / LOW
BYTE VALID
CONTROL
BYTE
CONTROL
BYTE
Figure 6. Conversion Timing Using External Acquisition Mode
2000
0
50
250
350
500
CLOCK PIN CAPACITANCE (pF)
INTERNAL
CLOCK
PERIOD
(ns)
100
150 200
300
1500
1000
Figure 7. Internal Clock Period vs. Clock Pin Capacitance
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