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參數資料
| 型號： | MAX199BMYI |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 模擬信號調理 |
| 英文描述： | Multi-Range (【4V, 【2V, +4V, +2V), +5V Supply, 12-Bit DAS with 8+4 Bus Interface |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, CDIP28 |
| 封裝： | 0.600 INCH, SIDE BRAZED, CERAMIC, DIP-28 |
| 文件頁數： | 11/16頁 |
| 文件大?。?/td> | 165K |
| 代理商： | MAX199BMYI |
How to Read a Conversion
A standard interrupt signal, INT, is provided to allow the
device to flag the μP when the conversion has ended
and a valid result is available. INT goes low when the
conversion is complete and the output data is ready
(Figures 5 and 6). It returns high on the first read cycle
or if a new control byte is written.
Cloc k Modes
The MAX199 operates with either an internal or an
external clock. Control bits (D6, D7) select either inter-
nal or external clock mode. Once the desired clock
mode is selected, changing these bits to program
power-down will not affect the clock mode. In each
mode, internal or external acquisition can be used. At
power-up, the MAX199 defaults to external clock mode.
Internal Clock Mode
Select internal clock mode to free the μP from the
burden of running the SAR conversion clock. To select
this mode, write the control byte with D7 = 0 and D6 = 1.
A 100pF capacitor between the CLK pin and ground
sets this frequency to 1.56MHz nominal. Figure 7
shows a linear relationship between the internal clock
period and the value of the external capacitor used.
M
Multi-Range (±4V, ±2V, +4V, +2V ),
+5V S upply, 12-Bit DAS with 8+4 Bus Interfac e
______________________________________________________________________________________
11
t
CS
t
CSWS
t
WR
t
ACQI
t
CONV
t
DH
t
DS
t
INT1
t
D0
t
D01
t
TR
t
CSHW
t
CSRS
t
CSRH
ACQMOD = "1"
CS
WR
D7–D0
INT
RD
HBEN
DOUT
ACQMOD = "0"
HIGH / LOW
HIGH-Z
HIGH-Z
HIGH / LOW
CBYTE
CBYTE
Figure 6. Conversion Timing Using External Acquisition Mode
2000
0
0
50
250
350
500
CLOCK PIN CAPACITANCE (pF)
I
100 150 200
300
1500
1000
Figure 7. Internal Clock Period vs. Clock Pin Capacitance
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