參數(shù)資料
型號: MAX2369EGM
廠商: Electronic Theatre Controls, Inc.
英文描述: PLASTIC ENCAPSULATED DEVICES
中文描述: 塑封器件
文件頁數(shù): 10/16頁
文件大?。?/td> 237K
代理商: MAX2369EGM
M
Complete Dual-Band
Quadrature Transmitter
10
______________________________________________________________________________________
The IFM register sets the main frequency divide ratio
for the IF PLL. The IFR register sets the reference fre-
quency divide ratio. The IF VCO frequency can be
determined by the following:
IF VCO frequency = f
REF
(IFM / IFR)
where f
REF
is the external reference frequency.
The operational control register (OPCTRL) controls the
state of the MAX2369. See
Table 3
for the function of
each bit.
The configuration register (CONFIG) sets the configura-
tion for the IF PLL and the baseband I/Q input levels
See
Table 4
for a description of each bit.
The test register is not needed for normal use.
Power Management
Bias control is distributed among several functional
sections and can be controlled to accommodate many
different power-down modes as shown in
Table 5
.
The shutdown control bit is of particular interest since it
differs from the
SHDN
pin. When the shutdown control
bit is active (SHDN_BIT = 0), the serial interface is left
active so that the part can be turned on with the serial
bus while all other functions remain shut off. In contrast,
Table 1. Register Power-Up Default States
Table 2. Register Initialization for F
REF
=
19.44MHz, F
IF
= 181.26MHz,
F
COMP
= 360kHz
Figure 1. Register Configuration
MSB
24 BIT REGISTER
LSB
DATA 20 BITS
B10
ADDRESS 4 BITS
A3
A2
B19
B18
B17
B16
B15
B14
B13
B12
B11
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
A1
A0
IFM DIVIDE RATIO REGISTER (14 BITS)
B9
B8
B7
ADDRESS
0
X
X
X
X
X
X
B13
B12
B11
B10
B6
B5
B4
B3
B2
B1
B0
0
1
0
IFR DIVIDE RATIO REGISTER (11 BITS)
B8
B7
B6
B5
ADDRESS
0
X
X
X
X
X
X
X
X
X
B10
B9
B4
B3
B2
B1
B0
0
1
1
CONTROL REGISTER (16 BITS)
B10
B9
B8
ADDRESS
1
X
X
X
X
B15
B14
B13
B12
B11
B7
B6
B5
B4
B3
B2
B1
B0
0
0
0
CONFIGURATION REGISTER (16 BITS)
B10
B9
B8
ADDRESS
1
X
X
X
X
B15
B14
B13
B12
B11
B7
B6
B5
B4
B3
B2
B1
B0
0
0
1
TEST REGISTER (8 BITS)
B5
B4
ADDRESS
1
X
X
X
X
X
X
X
X
X
X
X
X
B7
B6
B3
B2
B1
B0
0
1
1
X = DON
T CARE
REGISTER
IFM
IFR
DEFAULT
6519 dec
0492 dec
ADDRESS
0010
b
0011
b
FUNCTION
IF M divider count
IF R divider count
OPCTRL
892F hex
0100
b
Operational control
settings
CONFIG
D03F hex
0101
b
Configuration and
setup control
TEST
0000 hex
0111
b
Test-mode control
REGISTER
IFM
IFR
DEFAULT
1007 dec
0054 dec
ADDRESS
0010
b
0011
b
FUNCTION
IF M divider count
IF R divider count
OPCTRL
890F hex
0100
b
Operational control
settings
CONFIG
903D hex
0101
b
Configuration and
setup control
TEST
0000 hex
0111
b
Test-mode control
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