參數(shù)資料
型號: MAX271EWG+T
廠商: Maxim Integrated Products
文件頁數(shù): 3/16頁
文件大?。?/td> 0K
描述: IC FILTER LOWPASS PROG 24-SOIC
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 1,000
濾波器類型: 連續(xù)時間低通
頻率 - 截止或中心: 25kHz
濾波器數(shù): 2
濾波器階數(shù): 2nd
電源電壓: 4.74 V ~ 16 V,±2.37 V ~ 8 V
安裝類型: 表面貼裝
封裝/外殼: 24-SOIC(0.295",7.50mm 寬)
供應商設備封裝: 24-SOIC W
包裝: 帶卷 (TR)
11
Maxim Integrated
Digitally-Programmed, Dual
2nd-Order Continuous Lowpass Filter
MAX270/MAX271
Table 2. MAX271 P-Mode Interface
MAX270 Control Interlace
The A0 pin is a three-level input that selects the memory
addresses for updating cutoff frequency data in FP mode:
Figure 2 shows P-mode interface timing.
Connecting A0 to the negative supply selects pin-strap
mode. Pin-strap mode allows filter programming with
no timing requirements. Internal memory latches are
disabled, permitting filters A and B to be programmed
directly to fC data strapped on D0–D6. This mode dis-
ables CS and WR controls, and filters A and B are pro-
grammed to the same fC.
A low level on the SHDN pin shuts down all amplifiers
and disconnects OUTA, OUTB, and OP OUT. Current
consumption drops to less than 15A in this mode.
MAX271 Control Interlace
Connecting the MODE pin to GND or V- selects the
P mode. In this mode, addressable program memory
controls filter cutoff frequency programming and all T/H
functions, except T/H. See the Figure 2 for timing charac-
teristics. Table 2 describes available functions:
In FP mode, SHDN, T/H A/B, and T/H EN pins are dis-
abled. T/H remains enabled and performs the T/H track-
ing/holding function.
Tying MODE to V+ selects pin-strap mode. In this mode,
both memory latches are transparent, and data on D0–D6
controls the fC of filters A and 8 directly (filters A and 8
are programmed to the same fC). Pin strap D0–D6 for
operation without FP. A0, A1, CS, and WR are disabled.
X = Don't care
Figure 2. MAX270/MAX271 Digital Timing Diagram
CS
tWS
tWH
tWR
tAS
WR
ADDRESS
(A0, A1)
DATA
(D0-D6)
NOTE : ALL DIGITAL INPUTS ARE LEVEL-SENSITIVE. WHEN WR AND CS ARE BOTH LOW,
THE DATA INPUT LATCHES ARE TRANSPARENT. AND THE FILTERS ARE
PROGRAMMED TO THE DATA ON D0–D6
tAH
tDS
tDH
A0
SELECTS
Logic Low
Filter B
Logic High
Filter A
A1
A0
06
05
04
03
02
01
D0
FUNCTION
0
7-bit fC data
Selects filter A
0
1
7-bit fC data
Selects filter B
1
0
X
0
T/H OUT disabled
1
0
X
1
T/H OUT enabled
1
0
X
0
X
Selects OUTB as input to T/H
1
0
X
1
X
Selects OUTA as input to T/H
1
X
0
Filter shutdown mode. All outputs floated, 15A
max supply current
1
X
1
Removes filter from shutdown mode
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