參數(shù)資料
型號: MAX3232EEWE+T
廠商: Maxim Integrated Products
文件頁數(shù): 14/22頁
文件大?。?/td> 0K
描述: IC TXRX RS-232 LP 16-SOIC
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 1,000
類型: 收發(fā)器
驅(qū)動器/接收器數(shù): 2/2
規(guī)程: RS232
電源電壓: 3 V ~ 5.5 V
安裝類型: 表面貼裝
封裝/外殼: 16-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 16-SOIC W
包裝: 帶卷 (TR)
±15kV ESD-Protected, Down to 10nA, 3.0V to 5.5V,
Up to 1Mbps, True RS-232 Transceivers
Selector Guide
PART
NO. OF
DRIVERS/
RECEIVERS
LOW-POWER
SHUTDOWN
GUARANTEED
DATA RATE
(bps)
MAX3222E
2/2
250k
MAX3232E
2/2
250k
MAX3237E
(Normal)
5/3
250k
MAX3237E
(MegaBaud)
5/3
1M
MAX3241E
3/5
250k
MAX3246E
3/5
250k
Package Information
For the latest package outline information and land patterns,
go to www.maxim-ic.com/packages. Note that a “+”, “#”, or
“-” in the package code indicates RoHS status only. Package
drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
Ordering Information (continued)
PART
TEMP RANGE
PIN-PACKAGE
MAX3232ECTE+
0°C to +70°C
16 TQFN-EP**
(5mm x 5mm)
MAX3232ECUE+
0°C to +70°C
16 TSSOP
MAX3232ECUP+
0°C to +70°C
20 TSSOP
MAX3232EEAE+
-40°C to +85°C
16 SSOP
MAX3232EEWE+
-40°C to +85°C
16 Wide SO
MAX3232EEPE+
-40°C to +85°C
16 Plastic DIP
MAX3232EETE+
-40°C to +85°C
16 TQFN-EP**
(5mm x 5mm)
MAX3232EEUE+
-40°C to +85°C
16 TSSOP
MAX3232EEUP+
-40°C to +85°C
20 TSSOP
MAX3237ECAI+
0°C to +70°C
28 SSOP
MAX3237EEAI+
-40°C to +85°C
28 SSOP
MAX3241ECAI+
0°C to +70°C
28 SSOP
MAX3241ECWI+
0°C to +70°C
28 Wide SO
MAX3241ECUI+
0°C to +70°C
28 TSSOP
MAX3241ECTJ+
0°C to +70°C
32 TQFN-EP**
(7mm x 7mm)
MAX3241EEAI+
-40°C to +85°C
28 SSOP
MAX3241EEWI+
-40°C to +85°C
28 Wide SO
MAX3241EEUI+
-40°C to +85°C
28 TSSOP
MAX3246ECBX-T+
0°C to +70°C
6 x 6 UCSP
MAX3246EEBX-T+
-40°C to +85°C
6 x 6 UCSP
+
Denotes a lead(Pb)-free/RoHS-compliant package.
Requires solder temperature profile described in the Absolute
Maximum Ratings section. UCSP Reliability is integrally linked
to the user’s assembly methods, circuit board material, and
environment. Refer to the UCSP Reliability Notice in the UCSP
Reliability section of this datasheet for more information.
**EP = Exposed pad.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
20 TQFN
T2055+5
20 TSSOP
H20+2
20 SSOP
A20+1
18 Wide SO
W18+1
18 PDIP
P18+5
16 SSOP
A16+2
16 Wide SO
W16+3
16 PDIP
P16+1
16 TQFN
T1655+2
16 TSSOP
U16+1
28 SSOP
A28+1
28 Wide SO
W28+6
28 TSSOP
U28+2
32 TQFN
T3277+2
6x6 HCSP
B36+3
Refer to
Chip Information
PROCESS: BICMOS
Maxim Integrated
21
MAX3222E/MAX3232E/MAX3237E/
MAX3241E/MAX3246E
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