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參數(shù)資料
| 型號： | MAX3272AETP+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 8/14頁 |
| 文件大小： | 0K |
| 描述： | IC AMP LIMITING 20-TQFN |
| 產品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,500 |
| 類型： | 限幅放大器 |
| 應用： | 光纖學網絡 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-WFQFN 裸露焊盤 |
| 供應商設備封裝： | 20-TQFN-EP（4x4） |
| 包裝： | 帶卷 (TR) |
MAX3272/MAX3272A
+3.3V, 2.5Gbps Low-Power
Limiting Amplifiers
_______________________________________________________________________________________
3
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.0V to +3.6V, TA = -40°C to +85°C. Typical values are at VCC = +3.3V and TA = +25°C, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
High LOS Deassert Level
RTH = 80
(Notes 3, 10)
73
124.7
mVP-P
LOS Output High Voltage
Sinking 30A
2.4
V
LOS Output Low Voltage
Sourcing 1.2mA
0.4
V
Squelch Input Current
400
A
Note 1:
Dice are designed and guaranteed from -40°C to +85°C but are tested only at TA = +25°C.
Note 2:
Supply current measurement excludes the current of the CML output stage (16mA typical). See Figure 1, Power-Supply
Current Measurement.
Note 3:
Guaranteed by design and characterization.
Note 4:
Input edge speed is controlled using 4-pole, lowpass Bessel filters with bandwidth approximately 75% of the maximum
data rate.
Note 5:
Deterministic jitter is measured with a K28.5 pattern (0011 1110 1011 0000 0101). Deterministic jitter is the peak-to-peak
deviation from ideal time crossings, measured at the zero-level crossings of the differential output per ANSI X3.230, Annex A.
Note 6:
Random jitter is measured with the minimum input signal. For Fibre Channel and Gigabit Ethernet applications, the peak-
to-peak random jitter is 14.1 times the RMS random jitter.
Note 7:
Power-supply noise rejection (PSNR) is calculated by the equation PSNR = 20log (
VCC/(VOUT)), where VOUT is the
change in differential output voltage due to the power-supply noise,
VCC. See Power-Supply Noise Rejection vs.
Frequency in the Typical Operating Characteristics.
Note 8:
Hysteresis is defined as: 20 log(VLOS-DEASSERT/VLOS-ASSERT).
Note 9:
Response time to a 10dB change in input power. For the specification guaranteed, the power is assumed to switch back
and forth between two levels (separated by 10dB and equidistant from assert and deassert levels) outside of the two
hysteresis thresholds.
Note 10: All power-detect AC parameters are guaranteed with a 2
23 - 1 PRBS, 2.5Gbps input, with the longest possible run of 80CID.
Typical Operating Characteristics
(VCC = +3.3V, TA = +25°C, unless otherwise noted.)
600
650
700
750
800
850
900
950
1000
010
20304050
OUTPUT AMPLITUDE
vs. INPUT AMPLITUDE
MAX3272
toc01
VIN (mVP-P)
V
OUT
(mV
P-P
)
LEVEL = GND
LEVEL = OPEN
20
35
30
25
40
45
50
55
60
65
70
-40
10
-15
35
6085
SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
MAX3272
toc02
AMBIENT TEMPERATURE (
°C)
SUPPLY
CURRENT
(mA)
0
6
4
2
8
10
12
14
16
18
20
110100
1000
10,000
DETERMINISTIC JITTER
vs. INPUT AMPLITUDE
MAX3272
toc03
INPUT AMPLITUDE (mVP-P)
DETERMINISTIC
JITTER
(ps
P-P
)
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