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參數(shù)資料
| 型號： | MAX3295AUT+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 11/11頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TX RS485/422 DIFF SGL SOT23-6 |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 收發(fā)器 |
| 驅(qū)動器/接收器數(shù)： | 1/0 |
| 規(guī)程： | RS422，RS485 |
| 電源電壓： | 3.14 V ~ 3.47 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | SOT-23-6 |
| 供應(yīng)商設(shè)備封裝： | SOT-6 |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | MAX3295AUT+TDKR |
MAX3293/MAX3294/MAX3295
20Mbps, +3.3V, SOT23 RS-485/
RS-422 Transmitters
_______________________________________________________________________________________
9
Hot-Swap Input Circuitry
The MAX3293/MAX3294/MAX3295 enable input fea-
tures hot-swap capability. At the input, there are two
NMOS devices, M1 and M2 (Figure 6). When VCC
ramps from zero, an internal 10s timer turns on M2
and sets the SR latch, which also turns on M1.
Transistors M2, a 2mA current sink, and M1, a 100A
current sink, pull DE to GND through a 5.6k
Ω resistor.
M2 is designed to pull DE to the disabled state against
an external parasitic capacitance up to 100pF that may
drive DE high. After 10s, the timer deactivates M2
while M1 remains on, holding DE low against three-
state leakages that can drive DE high. M1 remains on
until an external source overcomes the required input
current. At this time, the SR latch resets and M1 turns
off. When M1 turns off, DE reverts to a standard, high-
impedance CMOS input. Whenever VCC drops below
1V, the hot-swap input is reset.
Hot-Swap Line Transient
During a hot-swap event when the driver is connected to
the line and is powered up, the driver must not cause the
differential signal to drop below 200mV. Figures 7, 8, and
9 show the results of the MAX3295 during power-up for
three different VCC ramp rates (0.1V/s, 1V/s, and
10V/s). The photos show the VCC ramp, the single-
ended signal on each side of the 100
Ω termination, as
well as the differential signal across the termination.
ESD Protection
Human Body Model
Figure 10 shows the Human Body Model, and Figure 11
shows the current waveform it generates when dis-
charged into low impedance. This model consists of a
100pF capacitor charged to the ESD voltage of interest,
which is then discharged into the device through a
1.5k
Ω resistor.
Figure 8. Differential Power-Up Glitch (1V/s)
Figure 9. Differential Power-Up Glitch (10V/s)
Figure 11. Current Waveform
DIFFERENTIAL POWER-UP GLITCH
(10V/
μs)
200ns/div
2V/div
VCC
Y
Z
Y-Z
0V
50mV/div
AC-COUPLED
50mV/div
AC-COUPLED
100mV/div
DIFFERENTIAL POWER-UP GLITCH
(1V/
μs)
1
μs/div
2V/div
VCC
Y
Z
Y-Z
0V
100mV/div
AC-COUPLED
100mV/div
AC-COUPLED
200mV/div
Figure 10. Human Body ESD Test
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
STORAGE
CAPACITOR
Cs
100pF
RC
1M
Ω
RD
1.5k
Ω
HIGH-
VOLTAGE
DC
SOURCE
DEVICE
UNDER
TEST
IP 100%
90%
36.8%
tRL
TIME
tDL
CURRENT WAVEFORM
PEAK-TO-PEAK RINGING
(NOT DRAWN TO SCALE)
Ir
10%
0V
AMPERES
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