參數(shù)資料
型號: MAX3454EEUD+
廠商: Maxim Integrated Products
文件頁數(shù): 14/19頁
文件大?。?/td> 0K
描述: IC TXRX USB ESD-PROT 14TSSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 96
類型: 收發(fā)器
規(guī)程: USB 2.0
電源電壓: 1.65 V ~ 3.6 V
安裝類型: 表面貼裝
封裝/外殼: 14-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 14-TSSOP
包裝: 管件
產(chǎn)品目錄頁面: 1407 (CN2011-ZH PDF)
MAX3453E–MAX3456E
±15kV ESD-Protected USB Transceivers
4
_______________________________________________________________________________________
Note 1: Parameters are 100% production tested at +25
°C, unless otherwise noted. Limits over temperature are guaranteed by design.
Note 2: Guaranteed by design, not production tested.
Note 3: Production tested to +2.7V for VL < +3.0V.
Note 4: Including external 27
series resistor.
TIMING CHARACTERISTICS
(VBUS = +4.0V to +5.5V or VTRM = +3.0V to +3.6V, VL = +1.65V to +3.6V, TA = TMIN to TMAX, unless otherwise noted. Typical values
are at VBUS = +5V, VL = +2.5V, and TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DRIVER CHARACTERISTICS (Full-Speed Mode, CL = 50pF)
Rise Time
tFR
10% to 90% of |VOHD - VOLD|, Figures 1, 6
4
20
ns
Fall Time
tFF
90% to 10% of |VOHD - VOLD|, Figures 1, 6
4
20
ns
Rise/Fall-Time Matching (Note 2)
tFR / tFF
Excluding the first transition from idle state,
Figures 1, 6
90
110
%
Output-Signal Crossover Voltage
(Note 2)
VCRS_F
Excluding the first transition from idle state,
Figures 2, 6
1.3
2.0
V
tPLH_DRV
Low-to-high transition, Figures 2, 6
18
Driver Propagation Delay
tPHL_DRV
High-to-low transition, Figures 2, 6
18
ns
tPHZ_DRV
High-to-off transition, Figure 3
20
ns
Driver Disable Delay
tPLZ_DRV
Low-to-off transition, Figure 3
20
ns
tPZH_DRV
Off-to-high transition, Figure 3
20
ns
Driver Enable Delay
tPZL_DRV
Off-to-low transition, Figure 3
20
ns
DRIVER CHARACTERISTICS (low-speed mode, CL = 200pF to 600pF, MAX3454E/MAX3455E/MAX3456E)
Rise Time
tLR
10% to 90% of |VOHD - VOLD|, Figures 1, 6
75
300
ns
Fall Time
tLF
90% to 10% of |VOHD - VOLD|, Figures 1, 6
75
300
ns
Rise/Fall-Time Matching
tLR / tLF
Excluding the first transition from idle state,
Figures 1, 6
80
125
%
Output-Signal Crossover Voltage
VCRS_L
Excluding the first transition from idle state,
Figures 2, 6
1.3
2.0
V
RECEIVER CHARACTERISTICS (CL = 15pF)
tPLH_RCV
Low-to-high transition, Figures 4, 6
22
Differential Receiver Propagation
Delay
tPHL_RCV
High-to-low transition, Figures 4, 6
22
ns
tPLH_SE
Low-to-high transition, Figures 4, 6
12
Single-Ended Receiver
Propagation Delay
tPHL_SE
High-to-low transition, Figures 4, 6
12
ns
tPHZ_SE
High-to-off transition, Figure 5
15
Single-Ended Receiver Disable
Delay
tPLZ_SE
Low-to-off transition, Figure 5
15
ns
tPZH_SE
Off-to-high transition, Figure 5
15
Single-Ended Receiver Enable
Delay
tPZL_SE
Off-to-low transition, Figure 5
15
ns
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