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參數(shù)資料
| 型號： | MAX349 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | Serially Controlled, Low-Voltage, 8-Channel Multiplexers(接通電阻100Ω,漏電流0.1nA,導(dǎo)通速率0.275μs,串行控制多路轉(zhuǎn)換器) |
| 中文描述： | 串行控制、低電壓、8通道和雙4通道多路復(fù)用器 |
| 文件頁數(shù)： | 14/20頁 |
| 文件大?。?/td> | 214K |
| 代理商： | MAX349 |
M
S erially Controlled, Low-Voltage,
8-Channel/Dual 4-Channel Multiplexers
14
______________________________________________________________________________________
_______________Detailed Desc ription
Basic Operation
The MAX349/MAX350 are 8-channel and dual 4-chan-
nel, serially controlled multiplexers (muxes). These
muxes are unusual in that any, all, or none of the input
channels can be directed to the output. All switches
are bidirectional, so inputs and outputs are inter-
changeable. When multiple inputs are connected to an
output, they are also connected to one another, sepa-
rated from each other only by the on-resistance of two
switches. Both parts require eight bits of serial data to
set all eight switches.
S erial Digital Interfac e
The MAX349/MAX350 interface can be thought of as an
8-bit shift register controlled by CS (Figure 2). While CS
is low, input data appearing at DIN is clocked into the
shift register synchronously with SCLK’s rising edge.
The input is an 8-bit word, each bit controlling one of
the eight switches (Tables 1 and 2). DOUT is the output
of the shift register, with data appearing synchronously
with SCLK’s falling edge. Data at DOUT is simply the
input data delayed by eight clock cycles.
When shifting the input data, D7 is the first bit in and
out of the shift register. While shifting data, the switches
remain in their previous configuration. When the eight
bits of data have been shifted in, CS is driven high.
This updates the new switch configuration and inhibits
further data from entering the shift register. Transitions
at DIN and SCLK have no effect when CS is high, and
DOUT holds the first input bit (D7) at its output.
More or fewer than eight clock cycles can be entered
during the CS low period. When this happens, the shift
register contains only the last eight serial data bits,
regardless of when they were entered. On the rising
edge of CS, all switches are set to the corresponding
states.
The MAX349/MAX350 three-wire serial interface is
compatible with SPI, QSPI, and Microwire standards. If
interfacing with a Motorola processor serial interface,
set CPOL = 0. The MAX349/MAX350 are considered to
be slave devices (Figures 2 and 3). At power-up, the
shift register contains all zeros, and all switches are off.
The latch that drives the analog switch is updated on
the rising edge of CS, regardless of SCLK’s state. This
meets all SPI and QSPI requirements.
Daisy Chaining
For a simple interface using several MAX349s and
MAX350s, “daisy chain” the shift registers as shown in
Figure 5. The CS pins of all devices are connected,
and a stream of data is shifted through the MAX349s or
MAX350s in series. When CS is brought high, all
switches are updated simultaneously. Additional shift
registers may be included anywhere in series with the
MAX349/MAX350 data chain. Note that the DOUT high
level is V+, which may not be compatible with
TTL/CMOS devices if V+ differs from the logic supply
for these other devices.
Addressable S erial Interfac e
When several serial devices are configured as slaves,
addressable by the processor, DIN pins of each
decode logic individually control CS of each slave
device. When a slave is selected, its CS pin is driven
low, data is shifted in, and CS is driven high to latch the
data. Typically, only one slave is addressed at a time.
DOUT is not used.
__________Applic ations Information
8x1 Multiplexer
The MAX349 can be programmed normally, with only
one channel selected for every eight clock pulses, or it
can be programmed in a fast mode, where channel
changing occurs on each clock pulse.
In fast mode, select the channels by sending a single high
pulse (corresponding to the selected channel) at DIN, and
a corresponding CS low pulse for every eight clock puls-
es. As SCLK clocks this through the register, each switch
sequences one channel at a time, starting with Channel 0.
D7
D6 D5 D4
MSB
LSB
D3 D2 D1 D0
DATA BITS FROM PREVIOUS DATA INPUT
DOUT POWER-UP DEFAULT: D7–D0 = 0
D6 D5 D4 D3 D2 D1 D0
D7
DOUT
DIN
SCLK
SWITCHES UPDATED
DATA CLOCKED IN
DATA CLOCKED OUT
CS
D7
INPUT DATA BITS
Figure 2. Three-Wire Interface Timing
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