參數(shù)資料
型號(hào): MAX3805ETE#G16
廠商: Maxim Integrated Products
文件頁數(shù): 7/10頁
文件大小: 0K
描述: IC EQUALIZER REC 10.7GBPS 16TQFN
標(biāo)準(zhǔn)包裝: 100
類型: 發(fā)射器
規(guī)程: 以太網(wǎng)
電源電壓: 3 V ~ 3.6 V
安裝類型: 表面貼裝
封裝/外殼: 16-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 16-TQFN-EP(3x3)
包裝: 管件
MAX3805
Input Stage with Equalization
The low-noise input stage of the MAX3805 includes two
amplifiers, one with flat frequency response and the
other with a highpass frequency response compensat-
ing for the loss characteristic of 6-mil FR-4 PC board
transmission line. A current-steering network, imple-
mented with a pair of variable attenuators feeding into a
common summing node, provides the means to contin-
uously vary the amount of equalization. The amount of
equalization is controlled by feedback from two power-
detector blocks that set the variable attenuators to
match the loss of a particular transmission path.
Dual Power-Detector Feedback Loop
The MAX3805 adapts the equalizer to a specific path
loss by sampling the output of the summing node with a
pair of frequency-dependent power detectors. The first
power detector has a lowpass bandwidth of 500MHz; the
second power detector has full bandwidth.
NRZ PRBS data has a sin2(f)/f2 spectral characteristic.
When this data is passed through a lossy FR-4 path,
high-frequency components are attenuated, while low-
10.7Gbps Adaptive Receive Equalizer
6
_______________________________________________________________________________________
MAX3805
CML IN
FLAT
AMP
BOOST
AMP
VARIABLE
ATTENUATOR
VARIABLE
ATTENUATOR
LIMITING
AMP
CML OUT
LF
POWER
DETECTOR
POWER
DETECTOR
LOOP
FILTER
SIGNAL
DETECT
LFPD
HFPD
SD
EN
SDO-
SDO+
SDI+
SDI-
VCC1
VCC
VCC2
Functional Diagram
50
Ω
50
Ω
ESD
STRUCTURES
VCC
VCC2
OUT+
OUT-
Figure 1. CML Output Structure
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