參數(shù)資料
型號(hào): MAX3873AETP+T
廠商: Maxim Integrated Products
文件頁數(shù): 10/10頁
文件大?。?/td> 0K
描述: IC RECOV/RETIME 2.5GBPS 20TQFN
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
類型: 時(shí)鐘和數(shù)據(jù)恢復(fù)(CDR)
PLL:
主要目的: SONET/SDH
輸入: CML
輸出: CML
電路數(shù): 1
比率 - 輸入:輸出: 1:2
差分 - 輸入:輸出: 是/是
頻率 - 最大: 2.67Gbps
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 20-TQFN-EP(4x4)
包裝: 帶卷 (TR)
MAX3873A
Low-Power, Compact 2.5Gbps or 2.7Gbps
Clock-Recovery and Data-Retiming IC
_______________________________________________________________________________________
9
Sinusoidal Jitter Tolerance and
Input Deterministic Jitter Trade-Offs
The MAX3873A has excellent jitter tolerance. Adding DJ
to the input will close the eye opening and result in
reduced sinusoidal jitter tolerance. It typically can toler-
ate more than 0.3UIP-P of 10MHz jitter when measured
with a 223 - 1 PRBS data stream with 0.4UI of determin-
istic jitter (DJ). This gives a total high-frequency jitter tol-
erance of 0.7UI. Refer to the Jitter Tolerance vs.
Pulse-Width Distortion and Jitter Tolerance vs.
Deterministic Jitter graphs in the
Typical Operating
Characteristics section.
Input and Output Terminations
The MAX3873A’s digital CML outputs (SDO+, SDO-,
SCLKO+, SCLKO-) have selectable output amplitude
controlled by the MODE input. If the SCLKO outputs
are not used, they can be disabled (see the Supply
Current vs. Temperature graph in the
Typical Operating
Characteristics section).
The structure of the high-speed digital outputs is shown
in Figure 8. The MODE input sets the current in the cur-
rent source, thereby controlling the output swing. The
SCLKEN input sets the current in the SCLKO current
source to 0mA, disabling the output.
The structure of the CML inputs (SDI±) is shown in Figure
9. Unless the CML input is DC-coupled to a CML output,
use AC-coupling with the CML inputs to avoid upsetting
the common-mode voltage.
Applications Information
Consecutive Identical Digits (CID)
The MAX3873A has a low phase and frequency drift in
the absence of data transitions. As a result, long runs of
consecutive zeros and ones can be tolerated while
maintaining a BER of less than 10-10. The CID tolerance
is tested using a 213 - 1 PRBS, substituting a long run
of zeros to simulate the worst case. A CID tolerance of
2000 bits is typical.
Exposed-Pad Package
The exposed-pad (EP), 20-pin QFN incorporates fea-
tures that provide a very low thermal-resistance path for
heat removal from the IC. The pad is electrical ground
on the MAX3873A and must be soldered to the circuit
board for proper thermal and electrical performance.
Layout
Circuit board layout and design can significantly affect
the MAX3873A’s performance. Use good high-frequency
design techniques, including minimizing ground induc-
tance and using controlled-impedance transmission
lines on the data and clock signals. Place power-supply
decoupling as close to the VCC pins as possible. Isolate
the input from the output signals to reduce feedthrough.
MAX3873A
SDI+
50
Ω
SDI-
VCC
50
Ω
MAX3873A
OUT-
MODE
SCLKEN
SCLKO ONLY
OUT+
VCC
50
Ω
50
Ω
Figure 8. CML Output Model
Figure 9. CML Input Model
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