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參數(shù)資料
| 型號： | MAX3886ETN+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 17/17頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MULTIRATE CDR SER/DES56-TQFN |
| 標準包裝： | 37 |
| 類型： | 時鐘和數(shù)據(jù)恢復（CDR），多路復用器 |
| PLL： | 是 |
| 主要目的： | 光纖網(wǎng)絡終端（ONT）應用，千兆位無源光纖網(wǎng)絡（GPON），寬帶無源光纖網(wǎng)絡（BPON） |
| 輸入： | CML，LVDS，LVPECL |
| 輸出： | CML，LVDS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 7:6 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 622MHz，2488Mbps |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-WFQFN 裸露焊盤 |
| 供應商設備封裝： | 56-TQFN-EP（8x8） |
| 包裝： | 管件 |
Detailed Description
The MAX3886 CDR/SerDes provides 2.488Gbps/
1.244Gbps/622Mbps clock and data recovery, plus 1:4
deserializer for continuous downstream data and 1:4
serializer for burst upstream data (Figure 4).
Specifically designed for GPON and BPON ONT appli-
cations, the serializer uses the recovered downstream
clock to serialize the upstream serial data (loop-timed
serialization). The upstream rate can be configured to
be either equal to the downstream rate (symmetric
operation) or a submultiple of the downstream rate
(asymmetric operation). A low-cost 19.4400MHz SMD-
type crystal or external LVCMOS source serves as the
CDR frequency reference, providing robust frequency
acquisition and lock detection.
A parallel rate reference clock output, derived from the
recovered downstream signal, is provided for use by
the MAC layer IC, and an integrated FIFO is provided
to deal with phase variation between the serializer and
MAC layer IC. Once the FIFO has been initialized, the
serializer tolerates up to one parallel UI phase differ-
ence between the read and write clocks. The FIFO cir-
cuitry includes an error output that indicates when the
FIFO attempts to read and write from the same location.
An integrated burst-enable signal path also includes
the FIFO to simplify upstream burst timing.
The deserializer parallel output clock can optionally be
configured for dual data rate (DDR) operation. The
high-speed CML-format serial-data interfaces are com-
patible with Maxim burst-mode laser drivers and both
CML and LVPECL limiting amplifiers. The parallel data
interfaces are LVDS format for compatibility with FPGAs
or ASICs.
Serial Input Clock/Data Recovery
Clock and data recovery is provided by a phase-locked
loop (PLL) with selectable 2.488GHz/1.244GHz/
622MHz operation. The operating frequency is con-
trolled by the three-state MVCO input. A phase detector
and filter generate error voltage proportional to the
phase difference between the internal VCO and the
input data, and feedback in the PLL drives the error
voltage to zero, aligning the recovered clock to the
center of the input data for retiming.
A frequency detector assists the PLL to “pull in” to the
serial data and generates the lock indicator signal on
the LOCK pin. When no valid input signal is present,
the LOCK output can oscillate (chatter) as the PLL
hunts for the input signal.
The PLL VCO and integrated loop filter implement a
second-order transfer function, with loop bandwidth
dependent on the VCO rate selected (e.g., 1.5MHz for
2.488Gbps). An external filter capacitor, connected
between CFIL and VCC sets the damping factor of the
PLL. All jitter specifications are based on an external
0.27F capacitor. Modifying the value of CFIL changes
jitter peaking, acquisition time, and loop stability but not
loop bandwidth.
PLL Reference Clock Oscillator
An integrated oscillator provides a reference clock sig-
nal for robust CDR acquisition and lock detection. This
oscillator requires a 19.4400MHz crystal connected
between RFCK1 and RFCK2, or an external LVCMOS
19.4400MHz clock source can be used. See the
Applications Information section for important informa-
tion about crystal selection and how to connect an
external clock source.
Deserializer and Parallel Output
The downstream data is deserialized, producing four
parallel LVDS outputs, PDO[3:0]±. The first serial data
bit received on the SDI input is the most significant bit
(MSB), which is routed to the parallel output PDO3. The
LVDS parallel output clock, PCKO, can be configured
for either full rate or half rate operation, as shown in the
timing diagrams of Figure 1. The PCKO rate is con-
trolled using the LVCMOS MDDR input. Set the MDDR
pin to logic high to clock out parallel data on each
edge of the PCKO clock.
Parallel Input, FIFO, and Serializer
Parallel data presented at the four LVDS data inputs
PDI[3:0]± is latched into the input register using the
LVDS parallel input clock PCKI and clocked out of the
ONT SerDes using the recovered serial clock. The par-
allel data bit PDI3 is the MSB and the first bit out of the
serial SDO output. For GPON and BPON ONT applica-
tions, the clock multiplier unit (CMU) frequency synthe-
sizer normally incorporated in SONET serializers is
eliminated, improving PON performance. Asymmetric
operation is configured using the LVCMOS MSYM input
(see Table 2). The parallel clock is also output on the
LVDS RCKO pins for use, if needed, by the MAC layer.
The serializer’s 4-bit-long FIFO accommodates phase
variation between RCKO and PCKI. PCKI provides the
FIFO write clock and the internal RCKO is the read
clock (loading the 4:1 serializer); this arrangement
allows the phase relationship between these two clocks
to vary ±1UI. In the event that valid read and write
clocks attempt to access the same FIFO address, this
error condition is indicated on the LVCMOS FERR out-
put. To initiate the FIFO or clear an error condition, the
LVCMOS FRST input must be asserted high for at least
4UI while valid clocks are present.
MAX3886
Multirate CDR with Integrated Serializer/Deserializer
for GPON and BPON ONT Applications
_______________________________________________________________________________________
9
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MAX3886ETN+ | 功能描述:串行器/解串器 - Serdes CDR w/Integrated Serial/Deserializer RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
| MAX3886ETN+T | 功能描述:串行器/解串器 - Serdes CDR w/Integrated Serial/Deserializer RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
| MAX388C/D | 功能描述:多路器開關 IC RoHS:否 制造商:Texas Instruments 通道數(shù)量:1 開關數(shù)量:4 開啟電阻（最大值）:7 Ohms 開啟時間（最大值）: 關閉時間（最大值）: 傳播延遲時間:0.25 ns 工作電源電壓:2.3 V to 3.6 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:UQFN-16 |
| MAX388CJN | 功能描述:多路器開關 IC RoHS:否 制造商:Texas Instruments 通道數(shù)量:1 開關數(shù)量:4 開啟電阻（最大值）:7 Ohms 開啟時間（最大值）: 關閉時間（最大值）: 傳播延遲時間:0.25 ns 工作電源電壓:2.3 V to 3.6 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:UQFN-16 |
| MAX388CPN | 功能描述:多路器開關 IC RoHS:否 制造商:Texas Instruments 通道數(shù)量:1 開關數(shù)量:4 開啟電阻（最大值）:7 Ohms 開啟時間（最大值）: 關閉時間（最大值）: 傳播延遲時間:0.25 ns 工作電源電壓:2.3 V to 3.6 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:UQFN-16 |
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