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參數(shù)資料
| 型號： | MAX3890ECB |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | +3.3V, 2.5Gbps, SDH/SONET 16:1 Serializer with Clock Synthesis and LVDS Inputs |
| 中文描述： | SERIAL TO PARALLEL/PARALLEL TO SERIAL CONVERTER, PQFP64 |
| 封裝： | 10 X 10 MM, 1 MM HEIGHT, MO-136AJ, TQFP-64 |
| 文件頁數(shù)： | 6/12頁 |
| 文件大?。?/td> | 155K |
| 代理商： | MAX3890ECB |
M
+3.3V, 2.5Gbps, SDH/SONET 16:1 Serializer
with Clock Synthesis and LVDS Inputs
6
_______________________________________________________________________________________
_______________Detailed Description
The MAX3890 converts 16-bit-wide, 155Mbps data to
2.5Gbps serial data (Figure 1). It is composed of a 16-
bit parallel input register, a 16-bit shift register, control
and timing logic, PECL output buffers, LVDS input/out-
put buffers, and a frequency-synthesizing PLL (consist-
ing of a phase/frequency detector, loop filter/amplifier,
voltage-controlled oscillator (VCO), and prescaler).
The PLL synthesizes an internal 2.5Gbps reference
used to clock the output shift register. This clock is
generated by locking onto the external 155.52MHz,
77.76MHz, 51.84MHz, or 38.88MHz reference-clock
signal (RCLK).
The incoming parallel data is clocked into the
MAX3890 on the rising transition of the parallel-clock-
input signal (PCLKI). Proper operation is ensured if the
parallel input register is latched within a window of time
(t
SKEW
) that is defined with respect to the parallel-
clock-output signal (PCLKO). PCLKO is the synthe-
sized 2.5Gbps internal serial-clock signal divided by
16. The allowable PCLKO-to-PCLKI skew is 0 to +4ns.
This defines a timing window after the PCLKO rising
edge, during which a PCLKI rising edge may occur
(Figure 2).
System Loopback
The MAX3890 is designed to allow system loopback test-
ing. The loopback outputs (SLBO+, SLBO-) of the
MAX3890 may be directly connected to the loopback
inputs of a deserializer (such as the MAX3880) for system
diagnostics. To enable the SLBO outputs, apply a TTL
logic-high signal to the SOS input.
Note:
The same signal
that controls the SOS enable input may also be used to
control the SIS enable input on the MAX3880.
MAX3890
PDI15+
PDI15-
16-BIT
PARALLEL
INPUT
REGISTER
PHASE/FREQ
DETECT
DIVIDE
BY 16
16-BIT
SHIFT
REGISTER
LVDS
LVDS
PCLKI-
PCLKI+
RCLKI-
RCLKI+
FIL+ FIL-CLKSET
PCLKO+ PCLKO-
VCO
PECL
SDO+
SDO-
SHIFT
LATCH
LVDS
PDI1+
PDI1-
LVDS
PDI0+
PDI0-
LVDS
LVDS
PRESCALER
FILTER
PECL
SCLKO+
SCLKO-
CML
SLBO+
SLBO-
SOS
PLL
Figure 1. Functional Diagram
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| MAX3890ECB+ | 制造商:Maxim Integrated Products 功能描述:LVDS SERLIZER 0.4V 64TQFP EP - Rail/Tube |
| MAX3890ECB+D | 功能描述:串行器/解串器 - Serdes 3.3V 2.5Gbps SDH/ SONET 16:1 Serial RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
| MAX3890ECB+T | 制造商:Maxim Integrated Products 功能描述:LVDS SERLIZER 0.4V 64TQFP EP - Tape and Reel |
| MAX3890ECB+TD | 功能描述:串行器/解串器 - Serdes 3.3V 2.5Gbps SDH/ SONET 16:1 Serial RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
| MAX3890ECB-D | 功能描述:串行器/解串器 - Serdes 3.3V 2.5Gbps SDH/ SONET 16:1 Serial RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
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