參數(shù)資料
型號: MAX4022EEE+T
廠商: Maxim Integrated Products
文件頁數(shù): 12/12頁
文件大小: 0K
描述: IC BUFFER R-R 16-QSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
放大器類型: 緩沖器
電路數(shù): 4
輸出類型: 滿擺幅
轉(zhuǎn)換速率: 600 V/µs
-3db帶寬: 200MHz
電流 - 輸入偏壓: 5.4µA
電壓 - 輸入偏移: 4000µV
電流 - 電源: 5.5mA
電流 - 輸出 / 通道: 120mA
電壓 - 電源,單路/雙路(±): 3.15 V ~ 11 V,±1.575 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-SSOP(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 16-QSOP
包裝: 帶卷 (TR)
MAX4014/MAX4017/MAX4019/MAX4022
Low-Cost, High-Speed, Single-Supply, Gain of +2
Buffers with Rail-to-Rail Outputs in SOT23
_______________________________________________________________________________________
9
Input Voltage Range and Output Swing
The input range for the MAX4014 family extends from
(VEE - 100mV) to (VCC - 2.25V). Input ground sensing
increases the dynamic range for single-supply applica-
tions. The outputs drive a 2k
load to within 60mV of
the power-suply rails. With heavier loads, the output
swing is reduced as shown in the Electrical Character-
istics and the Typical Operating Characteristics. As the
load increases, the input range is effectively limited by
the output-drive capability, since the buffers have a
fixed voltage gain of +2 or -1.
For example, a 50
load can typically be driven from
40mV above VEE to 1.6V below VCC, or 40mV to 3.4V
when operating from a single +5V supply. If the buffer is
operated in the noninverting, gain of +2 configuration
with the inverting input grounded, the effective input
voltage range becomes 20mV to 1.7V, instead of the
-100mV to 2.75V indicated by the Electrical Character-
istics. Beyond the effective input range, the buffer out-
put is a nonlinear function of the input, but it will not
undergo phase reversal or latchup.
Enable
The MAX4019 has an enable feature (EN_) that allows
the buffer to be placed in a low-power state. When the
buffers are disabled, the supply current will not exceed
550A per buffer.
As the voltage at the EN_ pin approaches the negative
supply rail, the EN_ input current rises. Figure 2 shows
a graph of EN_ input current versus EN_ pin voltage.
Figure 3 shows the addition of an optional resistor in
series with the EN pin, to limit the magnitude of the cur-
rent increase. Figure 4 displays the resulting EN pin
input current to voltage relationship.
20
-160
0
100
300
500
-100
-120
0
VIL (mV ABOVE VEE)
INPUT
CURRENT
(
A)
200
400
-60
-140
-20
-40
-80
Figure 2. Enable Logic-Low Input Current vs. Enable Logic-
Low Threshold
OUT
IN-
EN_
IN+
10k
ENABLE
MAX40_ _
500
500
Figure 3. Circuit to Reduce Enable Logic-Low Input Current
0
-10
0
100
300
500
-7
-8
-1
VIL (mV ABOVE VEE)
INPUT
CURRENT
(
A)
200
400
-3
-5
-9
-2
-4
-6
Figure 4. Enable Logic-Low Input Current vs. Enable Logic-
Low Threshold with 10k
Series Resistor
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