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參數(shù)資料
型號: MAX4238ASA+T
廠商: Maxim Integrated Products
文件頁數(shù): 4/9頁
文件大?。?/td> 0K
描述: IC AMP LOW-NOISE 8-SOIC
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
放大器類型: 通用
電路數(shù): 1
輸出類型: 滿擺幅
轉(zhuǎn)換速率: 0.35 V/µs
增益帶寬積: 1MHz
電流 - 輸入偏壓: 1pA
電壓 - 輸入偏移: 0.1µV
電流 - 電源: 600µA
電流 - 輸出 / 通道: 40mA
電壓 - 電源,單路/雙路(±): 2.7 V ~ 5.5 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 8-SOIC
包裝: 帶卷 (TR)
MAX4238/MAX4239
Ultra-Low Offset/Drift, Low-Noise,
Precision SOT23 Amplifiers
4
Maxim Integrated
ELECTRICAL CHARACTERISTICS
(2.7V
≤ VCC ≤ 5.5V, VCM = GND = 0V, VOUT = VCC/2, RL = 10kΩ connected to VCC/2, SHDN = VCC, TA = -40°C to +125°C, unless other-
wise noted.) (Note 5)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
TA = -40°C to +85°C
2.5
Input Offset Voltage
VOS
(Note 1)
TA = -40°C to +125°C
3.5
μV
Input Offset Drift
TCVOS
(Note 1)
10
nV/°C
Common-Mode Input Voltage
Range
VCM
Inferred from CMRR test
VGND
- 0.05
VCC
- 1.4
V
TA = -40°C to +85°C
115
Common-Mode Rejection Ratio
CMRR
VGND - 0.05V
VCM
VCC -
1.4V (Note 1)
TA = -40°C to +125°C
90
dB
Power-Supply Rejection Ratio
PSRR
2.7V
VCC
5.5V (Note 1)
120
dB
TA = -40°C to +85°C
125
RL = 10k ,
0.1V
VOUT
VCC - 0.1V
(Note 1)
TA = -40°C to +125°C
95
dB
0.1V
VOUT
VCC - 0.1V,
TA = -40°C to +85°C
120
Large-Signal Voltage Gain
AVOL
RL = 1k
(Note 1)
0.2V
VOUT
VCC - 0.2V,
TA = -40°C to +125°C
80
dB
VCC - VOH
20
RL = 10k
VOL
20
VCC - VOH
100
Output Voltage Swing
VOH/VOL
RL = 1k
VOL
100
mV
Output Leakage Current
0V
VOUT
VCC,
SHDN = GND
(Note 3)
2
μA
Supply Voltage Range
VCC
Inferred by PSRR test
2.7
5.5
V
SHDN = VCC, no load, VCC = 5.5V
900
Supply Current
ICC
SHDN = GND, VCC = 5.5V
2
μA
Shutdown Logic High
VIH
2.2
V
Shutdown Logic Low
VIL
0.7
V
Shutdown Input Current
0V
V SHDN VCC
2
μA
Note 1: Guaranteed by design. Thermocouple and leakage effects preclude measurement of this parameter during production
testing. Devices are screened during production testing to eliminate defective units.
Note 2: IN+ and IN- are gates to CMOS transistors with typical input bias current of 1pA. CMOS leakage is so small that it is
impractical to test and guarantee in production. Devices are screened during production testing to eliminate defective units.
Note 3: Leakage does not include leakage through feedback resistors.
Note 4: Overload recovery time is the time required for the device to recover from saturation when the output has been
driven to either rail.
Note 5: Specifications are 100% tested at TA = +25°C, unless otherwise noted. Limits over temperature are guaranteed by design.
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