參數(shù)資料
型號: MAX4238AUT+T
廠商: Maxim Integrated Products
文件頁數(shù): 8/9頁
文件大?。?/td> 0K
描述: IC AMP ULT HIGH PREC LN SOT23-6
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 1
放大器類型: 通用
電路數(shù): 1
輸出類型: 滿擺幅
轉(zhuǎn)換速率: 0.35 V/µs
增益帶寬積: 1MHz
電流 - 輸入偏壓: 1pA
電壓 - 輸入偏移: 0.1µV
電流 - 電源: 600µA
電流 - 輸出 / 通道: 40mA
電壓 - 電源,單路/雙路(±): 2.7 V ~ 5.5 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: SOT-23-6
供應商設備封裝: SOT-6
包裝: 標準包裝
其它名稱: MAX4238AUT+TDKR
MAX4238/MAX4239
Ultra-Low Offset/Drift, Low-Noise,
Precision SOT23 Amplifiers
8
Maxim Integrated
Output Overload Recovery
Autozeroing amplifiers typically require a substantial
amount of time to recover from an output overload. This
is due to the time it takes for the null amplifier to correct
the main amplifier to a valid output. The MAX4238/
MAX4239 require only 3.3ms to recover from an output
overload (see
Electrical Characteristics and Typical
Operating Characteristics).
Shutdown
The MAX4238/MAX4239 feature a low-power (0.1A)
shutdown mode. When SHDN is pulled low, the clock
stops and the device output enters a high-impedance
state. Connect SHDN to VCC for normal operation.
Applications Information
Minimum and Maximum Gain
Configurations
The MAX4238 is a unity-gain stable amplifier with a gain-
bandwidth product (GBWP) of 1MHz. The MAX4239 is
decompensated for a GBWP of 6.5MHz and is stable with
a gain of 10V/V. Unlike conventional operational ampli-
fiers, the MAX4238/MAX4239 have a maximum gain
specification. To maintain stability, set the gain of the
MAX4238 between AV = 1000V/V to 1V/V, and set the
gain of the MAX4239 between AV = 6700V/V and 10V/V.
ADC Buffer Amplifier
The low offset, fast settling time, and 1/f noise cancella-
tion of the MAX4238/MAX4239 make these devices
ideal for ADC buffers. The MAX4238/MAX4239 are well
suited for low-speed, high-accuracy applications such
as strain gauges (see
Typical Application Circuit).
Error Budget Example
When using the MAX4238/MAX4239 as an ADC buffer,
the temperature drift should be taken into account when
determining the maximum input signal. With a typical off-
set drift of 10nV/°C, the drift over a 10°C range is 100nV.
Setting this equal to 1/2LSB in a 16-bit system yields a
full-scale range of 13mV. With a single 2.7V supply, an
acceptable closed-loop gain is AV = 200. This provides
sufficient gain while maintaining headroom.
OUT
N.C.
GND
1
2
8
7
N.C.
VCC
IN-
IN+
SHDN
SO
TOP VIEW
3
4
6
5
MAX4238/
MAX4239
MAX4238/
MAX4239
GND
IN-
IN+
16
VCC
5
SHDN
OUT
SOT23
2
34
MAX4238/
MAX4239
6
V
CC
5
SHDN
4
IN-
OUT
GND
IN+
1
EP*
23
TDFN
(3mm x 3mm x 0.8mm)
+
*CONNECT EP TO GND.
Pin Configurations
Chip Information
PROCESS: BiCMOS
Package Information
For the latest package outline information and land patterns (foot-
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but the
drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE NO.
LAND
PATTERN NO.
6 SOT23
U6F-6
8 SO
S8-4
6 TDFN-EP
T633+2
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