
MAX4364/MAX4365
Clickless/Popless Operation
Proper selection of AC-coupling capacitors (CIN) and
CBIAS achieves clickless/popless shutdown and startup.
The value of CBIAS determines the rate at which the
midrail bias voltage rises on startup and falls when enter-
ing shutdown. The size of the input capacitor also affects
clickless/popless operation. On startup, CIN is charged
to its quiescent DC voltage through the feedback resistor
(RF) from the output. This current creates a voltage tran-
sient at the amplifier’s output, which can result in an
audible pop. Minimizing the size of CIN reduces this
effect, optimizing click-and-pop suppression.
Supply Bypassing
Proper supply bypassing ensures low-noise, low-distor-
tion performance. Place a 0.1F ceramic capacitor in
parallel with a 10F ceramic capacitor from VCC to
GND. Locate the bypass capacitors as close to the
device as possible.
Adding Volume Control
The addition of a digital potentiometer provides simple
volume control. Figure 3 shows the MAX4364/MAX4365
with the MAX5407 log taper digital potentiometer used
as an input attenuator. Connect the high terminal of the
MAX5407 to the audio input, the low terminal to ground
and the wiper to CIN. Setting the wiper to the top posi-
tion passes the audio signal unattenuated. Setting the
wiper to the lowest position fully attenuates the input.
Layout Considerations
Good layout improves performance by decreasing the
amount of stray capacitance and noise at the amplifier’s
inputs and outputs. Decrease stray capacitance by min-
imizing PC board trace lengths, using surface-mount
components and placing external components as close
to the device as possible. Also refer to the
Power
Dissipation section for heatsinking considerations.
1.4W and 1W, Ultra-Small, Audio Power
Amplifiers with Shutdown
12
______________________________________________________________________________________
OUT+
AUDIO
INPUT
OUT-
IN-
1H
W3
C
IN
R
F
R
IN
4L
MAX4364
MAX4365
MAX5407
Figure 3. MAX4364/MAX4365 and MAX5160 Volume Control
Circuit
Chip Information
PROCESS: BiCMOS
MAX
TDFN
2
7
SHDN
IN+
8
OUT-
1
1234
8765
BIAS
+
VCC
GND
3
6
OUT+
SHDN
OUT-
VCC OUT+
IN-
IN+
BIAS
GND
IN-
EP*
*CONNECT EP TO GND.
+
45
MAX4365
MAX4364
MAX4365
VCC
OUT+
IN-
1
2
8
7
OUT-
+
GND
BIAS
IN+
SHDN
SO
TOP VIEW
3
4
6
5
MAX4364
Pin Configurations