參數(shù)資料
型號: MAX4526ESA+T
廠商: Maxim Integrated Products
文件頁數(shù): 10/12頁
文件大?。?/td> 0K
描述: IC SWITCH DUAL SPDT 8SOIC
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
功能: 開關(guān)
電路: 2 x SPDT
導(dǎo)通狀態(tài)電阻: 175 歐姆
電壓電源: 單/雙電源
電壓 - 電源,單路/雙路(±): 4.5 V ~ 36 V,±4.5 V ~ 18 V
電流 - 電源: -400µA,700µA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 8-SOIC
包裝: 帶卷 (TR)
Power-Supply Considerations
Overview
The MAX4526/MAX4527 construction is typical of most
CMOS analog switches. It has three supply pins: V+, V-,
and GND. V+ and V- drive the internal CMOS switches
and set the analog-voltage limits on any switch.
Reverse ESD-protection diodes are internally connect-
ed between each analog signal pin, and both V+ and
V-. One of these diodes conducts if any analog signal
exceeds V+ or V-.
Virtually all of the analog leakage current is through the
ESD diodes to V+ or V-. Although the ESD diodes on a
given signal pin are identical and therefore fairly well
balanced, they are reverse biased differently. Each is
biased by either V+ or V- and the analog signal. This
means their leakages vary as the signal varies. The
dif-
ference in the two diode leakages from the signal path
to the V+ and V- pins constitutes the analog-signal-path
leakage current. All analog leakage current flows to the
supply terminals, not to the other switch terminal. This
explains how both sides of a given switch can show
leakage currents of either the same or opposite polarity.
There is no connection between the analog-signal paths
and GND. The analog-signal paths consist of an N-
channel and P-channel MOSFET with their sources and
drains paralleled and their gates driven out-of-phase to
V+ and V- by the logic-level translators.
V+ and GND power the internal logic and logic-level
translator and set the input logic threshold. The logic-
level translator converts the logic levels to switched V+
and V- signals to drive the analog switches’ gates. This
drive signal is the only connection between GND and
the analog supplies. V+ and V- have ESD-protection
diodes to GND. The logic-level input has ESD protec-
tion to V+ and to V- but not to GND, so the logic signal
can go below GND (as low as V-) when bipolar sup-
plies are used.
Increasing V- has no effect on the logic-level thresholds,
but it does increase the drive to the internal P-channel
switches, reducing the overall switch on-resistance. V-
also sets the negative limit of the analog-signal voltage.
The logic-level input pin, IN, has ESD-protection diodes
to V+ and V- but not to GND, so it can be safely driven
to V+ and V-. The logic-level threshold, VIN, is CMOS/
TTL compatible when V+ is between 4.5V and 36V
(see
Typical Operating Characteristics).
Bipolar Supplies
The MAX4526/MAX4527 operate with bipolar supplies
between ±4.5V and ±18V. However, since all factory
characterization is done with ±15V supplies, specifica-
tions at other supplies are not guaranteed. The V+ and
V- supplies need not be symmetrical, but their sum
cannot exceed the absolute maximum rating of 44V
(see
Absolute Maximum Ratings).
MAX4526/MAX4527
Phase-Reversal Analog Switches
_______________________________________________________________________________________
7
A
TIME WAVEFORMS
OUTPUT SPECTRUM
MODULATOR/DEMODULATOR CIRCUIT
LOGIC (CARRIER)
LOGIC
(CARRIER)
INPUT
OUTPUT
IN
B
A
X
Y
GND
V+
V-
V+
FREQUENCY
AMPLITUDE
LOWER
SIDEBAND
UPPER
SIDEBAND
SUPPRESSED CARRIER
B
X
Y
X-Y
(OUTPUT)
MAX4526
MAX4527
Figure 2. Balanced Modulator/Demodulator
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