參數(shù)資料
型號: MAX4540EAP+T
廠商: Maxim Integrated Products
文件頁數(shù): 4/20頁
文件大?。?/td> 0K
描述: IC MULTIPLEXER DUAL 4X1 20SSOP
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 2,000
功能: 多路復用器
電路: 2 x 4:1
導通狀態(tài)電阻: 75 歐姆
電壓電源: 單/雙電源
電壓 - 電源,單路/雙路(±): 2.7 V ~ 12 V,± 2.7 V ~ 6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-SSOP(0.209",5.30mm 寬)
供應商設備封裝: 20-SSOP
包裝: 帶卷 (TR)
MAX4539/MAX4540
Low-Voltage, Single 8-to-1 and
Dual 4-to-1 Cal-Multiplexers
12
______________________________________________________________________________________
Detailed Description
The MAX4539/MAX4540 are multiplexers with addition-
al calibration features. Internal resistor-dividers gener-
ate accurate voltage ratios from an external voltage
reference, allowing zero- and full-scale calibration of
ADC systems as well as facilitation of system self-moni-
toring. To access the resistor-dividers, assert the CAL
pin. When CAL and ENABLE are asserted, the three
address pins select one of the various resistor-divider
or external reference outputs. The MAX4539/MAX4540
also contain a LATCH input that allows the state of the
CAL and address signals to be captured.
Calibration Functions
The Gain Divider, Offset Divider, REFHI and REFLO
modes allow calibration of offset and gain errors in
ADC systems. The Gain Divider mode outputs a volt-
age ratio that is 4081/4096 of VREFHI - VREFLO, accu-
rate to 0.1/4096, or better than 15 bits. The Offset
Divider mode outputs a voltage ratio that is 15/4096 of
VREFHI - VREFLO, also accurate to 0.1/4096. The REFHI
mode allows the voltage on the REFHI pin to be
switched to the output. The REFLO mode allows the
voltage on the REFLO pin to be switched to the output.
Self-Monitoring Functions
The self-monitoring functions are intended to allow an
ADC to measure its own supply voltage. The MAX4539
has an internal divide-by-two resistor string between V+
and GND that is accurate to 8 bits (16/4096). It also has
a 5/8 resistor string between V+ and V- that is also
accurate to 8 bits. This divider string allows measure-
ment of the negative supply with a unipolar ADC. GND
can also be switched to the output, eliminating the
need for an additional multiplexer channel.
Applications Information
The MAX4539/MAX4540’s construction is typical of most
CMOS analog switches. There are three supply pins:
V+, V-, and GND. The positive and negative power sup-
plies provide drive to the internal CMOS switches and
set the limits of the analog voltage on any switch.
Reverse-biased ESD protection diodes are internally
connected between each analog signal pin and both V+
and V-. If the voltage on any pin exceeds V+ or V-, one
of these diodes will conduct. During normal operation,
these reverse-biased ESD diodes leak, forming the only
current drawn from V-.
Virtually all the analog-leakage current is through the
ESD diodes. Although the ESD diodes on a given sig-
nal pin are identical, and therefore fairly well bal-
anced, they are reverse-biased differently. Each is
biased by either V+ or V- and the analog signal. This
means their leakage varies as the signal varies. The
difference in the two-diode leakage from the signal
path to the V+ and V- pins constitutes the analog-
signal path leakage current. All analog-leakage cur-
rent flows to the supply terminals, not to the other
switch terminal, which explains how both sides of a
given switch can show leakage currents of either the
same or opposite polarity.
There is no connection between the analog-signal
paths and GND. The analog-signal paths consist of an
N-channel and P-channel MOSFET with their sources
and drains paralleled and their gates driven out of
phase with V+ and V- by the logic-level translators.
V+ and GND power the internal logic and logic-level
translators and set the input-logic thresholds. The logic-
level translators convert the logic levels to switched V+
and V- signals to drive the gates of the analog switches.
This drive signal is the only connection between the
logic supplies and the analog supplies. All pins have
ESD protection to V+ and to V-.
Increasing V- has no effect on the logic-level thresh-
olds, but it does increase the drive to the P-channel
switches, which reduces their on-resistance. V- also
sets the negative limit of the analog-signal voltage.
The logic-level thresholds are CMOS- and TTL- com-
patible when V+ is +5V. As V+ is raised, the threshold
increases slightly; when V+ reaches +12V, the level
threshold is about 3.2V. Although that is above the TTL
output high-level minimum of 2.4V, it is still compatible
with CMOS outputs.
Bipolar-Supply Operation
The MAX4539/MAX4540 operate with bipolar supplies
between ±2.7V and ±6V. The V+ and V- supplies need
not be symmetrical, but their sum cannot exceed the
absolute maximum rating of 13V.
Note: Do not connect the MAX4539/MAX4540 V+ pin
to +3V AND connect the logic-level input pins to TTL
logic-level signals. TTL logic-level outputs can
exceed the absolute maximum ratings, which will
cause damage to the part and/or external circuits.
Caution: The absolute maximum V+ to V- differential
voltage is 13V. Typical “±6-Volt” or “12-Volt” sup-
plies with ±10% tolerances can be as high as 13.2V.
This voltage can damage the MAX4539/MAX4540.
Even ±5% tolerance supplies may have overshoot
or noise spikes that exceed 13V.
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