參數(shù)資料
型號: MAX4565EAP+T
廠商: Maxim Integrated Products
文件頁數(shù): 2/16頁
文件大?。?/td> 0K
描述: IC SW QUAD VIDEO BIDIRECT 20SSOP
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 2,000
功能: 視頻開關
電路: 4 x SPST - NO
導通狀態(tài)電阻: 60 歐姆
電壓電源: 單/雙電源
電壓 - 電源,單路/雙路(±): 2.7 V ~ 12 V,± 2.7 V ~ 6 V
電流 - 電源: 1µA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-SSOP(0.209",5.30mm 寬)
供應商設備封裝: 20-SSOP
包裝: 帶卷 (TR)
MAX4565/MAX4566/MAX4567
Single-Supply Operation
The MAX4565/MAX4566/MAX4567 operate from a sin-
gle supply between +2.7V and +12V when V- is con-
nected to GND. All of the bipolar precautions must be
observed. Note, however, that these parts are opti-
mized for ±5V operation, and most AC and DC charac-
teristics are degraded significantly when departing
from ±5V. As the overall supply voltage (V+ to V-) is
lowered, switching speed, on-resistance, off isolation,
and distortion are degraded. (See
Typical Operating
Characteristics.)
Single-supply operation also limits signal levels and
interferes with grounded signals. When V- = 0V, AC sig-
nals are limited to -0.3V. Voltages below -0.3V can be
clipped by the internal ESD-protection diodes, and the
parts can be damaged if excessive current flows.
Power Off
When power to the MAX4565/MAX4566/MAX4567 is off
(i.e., V+ = 0V and V- = 0V), the Absolute Maximum
Ratings still apply. This means that neither logic-level
inputs on IN_ nor signals on COM_, NO_, or NC_ can
exceed ±0.3V. Voltages beyond ±0.3V cause the inter-
nal ESD-protection diodes to conduct, and the parts
can be damaged if excessive current flows.
Grounding
DC Ground Considerations
Satisfactory high-frequency operation requires that
careful consideration be given to grounding. For most
applications, a ground plane is strongly recom-
mended, and all GND_ pins should be connected to
it with solid copper. While the V+ and V- power-supply
pins are common to all switches in a given package,
each switch has separate ground pins that are not
internally connected to each other. This contributes to
the overall high-frequency performance and provides
added flexibility in some applications, but it can cause
problems if it is overlooked. All the GND_ pins have
ESD diodes to V+ and V-.
In systems that have separate digital and analog (sig-
nal) grounds, connect these switch GND_ pins to ana-
log ground. Preserving a good signal ground is much
more important than preserving a digital ground.
The logic-level inputs, IN_, have voltage thresholds
determined by V+ and GND_. (V- does not influence
the logic-level threshold.) With +5V and 0V applied to
V+ and GND_, the threshold is about 1.6V, ensuring
compatibility with TTL- and CMOS-logic drivers.
The various GND_ pins can be connected to separate
voltage potentials if any or all of the logic-level inputs is
not a normal logic signal. (The GND_ voltages cannot
exceed (V+ - 2V) or V-.) Elevating GND_ reduces off
isolation. For example, using the MAX4565, if GND2–
GND6 are connected to 0V and GND1 is connected to
V-, then switches 2, 3, and 4 would be TTL/CMOS com-
patible, but switch 1 (IN1) could be driven with the rail-
to-rail output of an op amp operating from V+ and V-.
Note, however, that IN_ can be driven more negative
than GND_, as far as V-. GND_ does not have to be
removed from 0V when IN_ is driven from bipolar
sources, but the voltage on IN_ should never exceed V-.
GND_ should be separated from 0V only if the logic-
level threshold has to be changed.
Any GND_ pin not connected to 0V should be
bypassed to the ground plane with a surface-mount
10nF capacitor to maintain good RF grounding. DC
current in the IN_ and GND_ pins is less than 1nA, but
increases with switching frequency.
On the MAX4565 only, two extra ground pins—GND5
and GND6—are provided to improve isolation and
crosstalk. They are not connected to the logic-level cir-
cuit. These pins should always be connected to the
ground plane with solid copper.
AC Ground and Bypassing
A ground plane is mandatory for satisfactory high-
frequency operation. (Prototyping using hand wiring or
wire-wrap boards is strongly discouraged.) Connect all
0V GND_ pins to the ground plane with solid copper.
(The GND_ pins extend the high-frequency ground
through the package wire-frame, into the silicon itself,
thus improving isolation.) The ground plane should be
solid metal underneath the device, without interruptions.
There should be no traces under the device itself. For
DIP packages, this applies to both sides of a two-
sided board. Failure to observe this will have a minimal
effect on the “on” characteristics of the switch at high
frequencies, but it will degrade the off isolation and
crosstalk.
Bypass all V+ and V- pins to the ground plane with sur-
face-mount 10nF capacitors. For DIP packages, mount
the capacitors as close as possible to the pins on the
same side of the board as the device. Do not use
feedthroughs or vias for bypass capacitors.
For surface-mount packages, bypass capacitors
should be mounted on the opposite side of the board
from the device. In this case, use short feedthroughs or
vias, directly under the V+ and V- pins. Any GND_ pin
not connected to 0V should be similarly bypassed. If V-
is 0V, connect it directly to the ground plane with solid
copper. Keep all leads short.
Quad/Dual, Low-Voltage,
Bidirectional RF/Video Switches
10
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