參數(shù)資料
型號: MAX4583EEE+T
廠商: Maxim Integrated Products
文件頁數(shù): 17/17頁
文件大?。?/td> 0K
描述: IC SWITCH TRIPLE SPDT 16QSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
功能: 開關(guān)
電路: 3 x SPDT
導(dǎo)通狀態(tài)電阻: 80 歐姆
電壓電源: 單/雙電源
電壓 - 電源,單路/雙路(±): 2 V ~ 12 V,±2 V ~ 6 V
電流 - 電源: 1µA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-SSOP(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 16-QSOP
包裝: 帶卷 (TR)
MAX4581/MAX4582/MAX4583
Low-Voltage, CMOS Analog
Multiplexers/Switches
_______________________________________________________________________________________
9
X
H
Table 1. Truth Table/Switch Programming
X
All switches open
L
X–X0
X–X0,
Y–Y0
X–X0,
Y–Y0,
Z–Z0
L
H
X–X1
X–X1,
Y–Y1
X–X1,
Y–Y0,
Z–Z0
L
H
X–X3
X–X3,
Y–Y3
X–X1,
Y–Y1,
Z–Z0
H
L
X–X2
X–X2,
Y–Y2
X–X0,
Y–Y1,
Z–Z0
L
H
X–X5
X–X1,
Y–Y1
X–X1,
Y–Y0,
Z–Z1
L
X–X4
X–X0,
Y–Y0
X–X0,
Y–Y0,
Z–Z1
H
L
H
L
H
X–X7
X–X3,
Y–Y3
X–X1,
Y–Y1,
Z–Z1
H
L
X–X6
X–X2,
Y–Y2
X–X0,
Y–Y1,
Z–Z1
H
L
H
L
X = Don’t care
*
C not present on MAX4582.
Note: Input and output pins are identical and interchangeable. Either may be considered an input or output; signals pass equally
well in either direction.
ON SWITCHES
SELECT INPUTS
B
A
MAX4581
MAX4582
MAX4583
C*
ENABLE
INPUT
will conduct. During normal operation, these and other
reverse-biased ESD diodes leak, forming the only cur-
rent drawn from VCC or VEE.
Virtually all the analog leakage current comes from the
ESD diodes. Although the ESD diodes on a given sig-
nal pin are identical and therefore fairly well balanced,
they are reverse biased differently. Each is biased by
either VCC or VEE and the analog signal. This means
their leakages will vary as the signal varies. The
differ-
ence in the two diode leakages to the VCC and VEE
pins constitutes the analog-signal-path leakage current.
All analog leakage current flows between each pin and
one of the supply terminals, not to the other switch ter-
minal. This is why both sides of a given switch can
show leakage currents of either the same or opposite
polarity.
There is no connection between the analog-signal
paths and GND.
VCC and GND power the internal logic and logic-level
translators, and set the input logic limits. The logic-level
translators convert the logic levels into switched VCC
and VEE signals to drive the gates of the analog sig-
nals. This drive signal is the only connection between
the logic supplies and signals and the analog supplies.
VCC and VEE have ESD-protection diodes to GND.
The logic-level thresholds are TTL/CMOS compatible
when VCC is +5V. As VCC rises, the threshold increases
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