參數(shù)資料
型號(hào)： MAX4589CPP
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： 運(yùn)動(dòng)控制電子
英文描述： Low-Voltage, High-Isolation, Dual 2-Channel RF/Video Multiplexer
中文描述： 2-CHANNEL, VIDEO MULTIPLEXER, PDIP20
封裝： 0.300 INCH, PLASTIC, MO-058AB, MS-001AE, DIP-20
文件頁(yè)數(shù)： 3/20頁(yè)
文件大?。?/td> 309K
代理商： MAX4589CPP
M
Low-Voltage, High-Isolation,
Dual 2-Channel RF/Video Multiplexer
_______________________________________________________________________________________
3
V
NO_
= 1V
RMS
, f = 10MHz,
Figure 5
V
NO_
= 1V
RMS
, f = 10MHz,
all channels off, Figure 5
V
NO_
= 3V, V+ = 5.5V,
V- = -5.5V, Figure 2
V
COM_
= 0, f
IN
= 1MHz, Figure 4
V
COM_
= 0, f
IN
= 1MHz, Figure 4
V
NO_
= 3V, V+ = 4.5V,
V- = -4.5V, Figure 1
V
NO_
= 3V, V+ = 4.5V,
V- = -4.5V, Figure 1
I
SOURCE
= -1mA
V
NO_
= 0, f
IN
= 1MHz, Figure 4
C
L
= 1.0nF, V
NO_
= 0,
R
S
= 0, Figure 3
CONDITIONS
dB
-70
V
CT
Channel-to-Channel Crosstalk
dB
-74
V
ISO
Off-Isolation (Note 7)
pF
6
C
COM_(ON)
COM_ On-Capacitance
pF
4
C
COM_(OFF)
COM_ Off-Capacitance
pF
2
C
NO_(OFF)
NO_ Off-Capacitance
pC
15
Q
Charge Injection
+25°C
+25°C
ns
10
180
t
BBM
Break-Before-Make Time Delay
(Note 3)
ns
150
300
350
t
OFF
Turn-Off Time
ns
380
550
600
t
ON
Turn-On Time
V
V
L
- 1
V
OH
DOUT Logic High Output
SWITCH DYNAMIC CHARACTERISTICS
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
C, E
+25°C
+25°C
+25°C
C, E
+25°C
C, E
C, E
+25°C
+25°C
T
A
I
SINK
= 3.2mA
V
0.4
V
OL
DOUT Logic Low Output
C, E
ELECTRICAL CHARACTERISTICS—Dual Supplies (continued)
(V+ = V
L
= +4.5V to +5.5V, V- = -4.5V to -5.5V, V
INH
= +2.4V, V
INL
= +0.8V, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical val-
ues are at T
A
= +25°C, V+ = V
L
= +5V, V- = -5V.) (Note 2)
Figure 5
MHz
200
150
20
15
BW
-3dB Bandwidth
+25°C
2-channel mode
4-channel mode
2-channel mode
Figure 5
MHz
BW
-0.1dB Bandwidth
+25°C
4-channel mode
Figure 6
Figure 6
Figure 6
Figure 6
ns
ns
ns
ns
80
0
80
80
t
DS
t
DH
t
L
t
RS
A_, EN to
LE
Rise Setup Time
A_, EN to
LE
Rise Hold Time
LE
Low Pulse Width
RS
Low Pulse Width
SERIAL-INTERFACE TIMING
C, E
C, E
C, E
C, E
Figure 7
Figure 7
Figure 7
Figure 7
Figure 7
MHz
ns
ns
ns
ns
6.25
f
CLK
t
CH
t
CL
t
DS
t
DH
Operating Frequency
SCLK Pulse Width High
SCLK Pulse Width Low
DIN to SCLK Rise Setup Time
DIN to SCLK Rise Hold Time
C, E
C, E
C, E
C, E
C, E
80
80
60
0
LOGIC OUTPUT (SERIAL INTERFACE)
PARALLEL-INTERFACE TIMING
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